Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Abstract

Abstract. Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 µm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems.

High Performance Low Cost Video Analysis Core for Smart Camera Chips in Distributed Surveillance Network

“…In Fig. 13, the [13] 55,066 Chien [8] 16,720 Proposed 8,640 Monitor of MPEG and BLIFO0,which is our own sequence.…”

“…7 (b). To be fair on comparison with [8], here we apply the same technique on the PE design, which is the logics of stagel and stage2 in Fig. 12.…”

“…The stagel logics are used to generate partial results of each column, while the stage2 logics would merge the corresponding partial column results into the temporary result corresponding to each window. The remaining logic (MUXs and inverters) are used to reconfigure the hardware, which can provide four configurations: dilation, erosion, conditional erosion, and no operation to be fairly compared with [8]. The image boundary conditions handling circuits are also included in this figure, which include the AND gates and the signals VCO, VC1, VC2, HCO, and HC7 [8].…”

“…5. The segmentation module can be designed with [8]. Beside of the segmentation hardware accelerator, we also design a low cost architecture for hardware accelerators of CCL and SKN, which are both window operations, by subword level parallelism.…”

“…The Proposed Architecture for Video Segmentation Accelerator The proposed hardware architecture of the video segmentation accelerator (SEG) is shown in Fig. 6, which is based on our previous work [8], where our segmentation algorithm with background registration technique [6] is implemented. It is a gray-scale datapath and binary datapath hybrid architecture, and it is also a fixed function and programmable function hybrid architecture.…”