Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

Abstract

Purpose In most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures. Design/methodology/approach The performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture. Findings A comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement. Originality/value This paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

Gecikme, alan, güç ve enerji açısından hibrit paralel toplayıcılar için karşılaştırmalı bir performans değerlendirmesi

“…Sözde taşıma üretimi ve yayılma (ti), üretme (gi), yarı toplam (Hi) sinyallerin ön işlemesi aynı anda gerçekleşir. Son taşıma sinyallerinin önek hesaplaması, 1 ve 2 seviyelerinde gerçekleştirilir[21,27]. Radix-8 booth kodlamalı 3x nesil için enerji verimli paralel hibrit toplayıcı mimarisi Şekil 16'da gösterilmektedir.…”