Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits

Shu, Li; Zhang, Tong

doi:10.1109/iccd.2007.4601955

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Proposed Repair Techniques1

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Cited by 2 publications

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“…The tagging mechanism for the proposed techniques is relatively simple and can be accommodated in the LUT unit decoder circuit. Since the primary motivation of this work is to propose repair techniques for a defect tolerant hybrid nano/CMOS computational architecture, we have not focussed on the fabrication issues related to LUT architecture and interconnect issues between nano and CMOS components [26]. For example, one way to implement CMOS tags can be to use nanoscale FET as a capacitive switching device [25], [27].…”

Section: Proposed Repair Techniquesmentioning

confidence: 99%

Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture

Srivastava

Melouki

Al-Hashimi

2011

IEEE Trans. Nanotechnology

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Abstract-We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques.

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Section: Proposed Repair Techniquesmentioning

confidence: 99%