Hybrid self-controlled precharge-free CAM design for low power and high performance

Satyanarayana, S. V. V.; Sridevi, Sriadibhatla

doi:10.3906/elk-1807-271

Cited by 9 publications

(2 citation statements)

References 17 publications

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“…In this paper [6], They proposed architecture utilizes LUTs (from SLICEM of FPGA) as a memory element to emulate RAM-based CAM with a novel arrangement to save power. The average power consumption of the whole architecture is reduced by 30% compared to the state-of-the-art FPGA based CAMs.…”

Section: Literature Reviewmentioning

confidence: 99%

Fast Mapping and Updating of Content-Addressable Memories - A Survey

2023

IRJMETS

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In a variety of applications, including IP filtering, data compression, and artificial neural networks, contentaddressable memory (CAMs) are used because of their quick lookup times. Instead of using an address, CAM can perform a lookup in a single clock cycle using the content. However, the slower mapping and updating processes in CAM emulation cause an undesirable response in real-time applications. The relationship between the CAM depth in the schemes and the update mechanism's decreased response time. Lookup tables, slice registers, and block random access memory (RAMs) are all effectively used in the fast mapping and updating algorithms for a binary CAM (FMU-BiCAM). Here, the CAM key is applied directly to an address, assisting in changing the contents of memory units. When the CAM is remapped words including the updating word, CAMs in the literature consume the whole CAM depth, resulting in increased update latency.

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Section: Literature Reviewmentioning

confidence: 99%

Fast Mapping and Updating of Content-Addressable Memories - A Survey

2023

IRJMETS

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“…This design is developed to improve the performance but at the cost of power consumption. To avoid the draw backs of SCPF-CAM and PF-CAM, a hybrid self-controlled precharge-free (HSCPF) CAM was proposed [11], which exhibits better energy delay product (EDP).…”

Section: Content Addressable Memorymentioning

confidence: 99%

Dual bit control low-power dynamic content addressable memory design for IoT applications

Satyanarayana¹,

Sridevi²

2021

Turk J Elec Eng & Comp Sci

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The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speed applications. Many search engines of IoT applications require low power consumption and high-speed content addressable memory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardware device used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper, a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. The proposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match line output for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design to perform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented using a CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. The simulation results show that the proposed design reduces power and search delay when compared to conventional DCAM designs.

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