Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

Abstract

A novel hybrid number representation is proposed in this paper. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike.We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the tradeoffs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times.In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

“…where the computed sum need not belong to the same hybrid-redundant number system as the operands (i.e., redundant positions of the result are shifted one position to the left of the redundant position of the operands). This property forces the use of additional hardware for format conversion [6], [10]. We offer representationally closed addition schemes for all the previously studied variants of hybrid-redundant number systems and our new symmetric variants in Section 4.…”

Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology

“…The second property implies that the code is unique. However, if this property is relaxed, this representation is called the minimal signed digit (MSD) representation, which has as many non-zeros as the CSD representation, but provides multiple representations for a constant [2,3]. Efficient multipliers can be implemented using CSD code and this has been adopted by a number of researchers [4][5][6].…”

Area×delay (A·T) efficient multiplier based on an intermediate hybrid signed-digit (HSD-1) representation

“…A Hybrid Signed Digit (HSD) representation was introduced in [11]. It lets some of the digits remain unsigned bits, thereby reducing the total number of bit lines.…”

“…Of particular interest is the HSD-1 format wherein, every alternate digit is signed and the remaining digits are unsigned (ordinary) bits. The Least Significant Bit (LSB) is unsigned and the Most Significant Bit (MSB) has to be a signed digit (reasons for this and other details about HSD representations can be found in [11]). Note that the number of bits required to represent a partial sum in the HSD-1 format is only 3 4 th the corresponding number of bits required by the FSD format (since alternate positions in the HSD-1 format are unsigned bits).…”