Hybrid SSD with PCM

Liu, Yining; Zhou, Chuangshi; Xiao-hua, Cheng

doi:10.1109/nvmts.2011.6137103

Cited by 5 publications

(7 citation statements)

References 1 publication

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“…This result cannot be achieved with existing SSD based on NAND Flash memories, since this performance is orders of magnitude faster than existing Flash based SSDs, resulting in a new class of block storage devices. Moreover, innovative hybrid SSD architectures have been recently proposed to take advantage of PCM speed and non-volatility, in particular to improve the reliability of actual SSD based on NAND Flash [80], [81].…”

Section: Benchmarking Pcm With Dram and Nand Flashmentioning

confidence: 99%

“…PCMs or STT-MRAMs can be integrated in hybrid SSDs to greatly help in the power loss protection and data recovery. In [80], two hybrid SSD architectures based on PCM were debated, although STT-MRAM could fit as well in the design with even superior characteristics. Fig.…”

Section: B the Power Loss Recovery Casementioning

confidence: 99%

“…Upon a power fault event no data flush from PCM/STT-MRAM to NAND Flash is requested thanks to the non-volatility of the former memory, therefore the time needed for a flush operation is null. On the contrary, in state-of-the-art SSD architectures this time can be calculated as [80]: where N data is the amount of data cached in DRAM, N map is the amount of FTL's metadata in DRAM, T N AN D is the time needed to write the cached data to NAND Flash, and T F T L is the time requested by the FTL to compute where the data needs to be stored according to the wear-out and utilization statistics of the NAND Flash, respectively. When the PCM/STT-MRAM is used as an auxiliary cache memory integrated in the disk along with the DRAM its role is to store the mapping tables and the FTL's metadata that will be flushed to DRAM at the system power on.…”

Section: B the Power Loss Recovery Casementioning

confidence: 99%

“…This equation holds true in the assumption of a perfect Wear Levelling scheme [118]. When a hybrid SSD architecture is considered, the Lif etime can be extended by a multiplication factor γ that has been demonstrated in [80] to be:…”

Section: B the Power Loss Recovery Casementioning

confidence: 99%

“…. Hybrid SSD architectures for power loss protection either using PCM or STT-MRAM as a full DRAM replacement or as auxiliary cache memories to complement DRAM (architecture idea taken from[80]).…”

mentioning

confidence: 99%

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Phase Change and Magnetic Memories for Solid-State Drive Applications

et al. 2017

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The state-of-the-art solid-state drives (SSDs) now heterogeneously integrate nand Flash and dynamic random access memories (DRAMs) to partially hide the limitation of the nonvolatile memory technology. However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, nand Flash are becoming a serious bottleneck. DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. Several emerging memory technologies are candidate to replace them, namely the storage class memories. Phase change memories and magnetic memories fall into this category. In this work, we review both technologies from the perspective of their possible application in future disk drives, opening up new computation paradigms as well as improving the storage characteristics in terms of latency and reliability

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Section: Benchmarking Pcm With Dram and Nand Flashmentioning

confidence: 99%

Section: B the Power Loss Recovery Casementioning

confidence: 99%

Section: B the Power Loss Recovery Casementioning

confidence: 99%

Section: B the Power Loss Recovery Casementioning

confidence: 99%

mentioning

confidence: 99%

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Phase Change and Magnetic Memories for Solid-State Drive Applications

et al. 2017

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Phase change memory applications: the history, the present and the future

Fantini

2020

J. Phys. D: Appl. Phys.

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50 years from the discovery of the phase change memory (PCM) is a sufficient time frame to see the steps of this technology with a historical perspective. So, a historical review of the PCM from its first proof of concept up to the most recent achievements of the research is provided. A parallel historical glance to the product development is also proposed as background to lead the discussion on the opportunities that PCM can bring in the actual scenario of memory eco-system. Against the dream of PCM as universal memory, this paper offers guidelines for PCM applications in the widespread landscape separating the short-time memory (like DRAM, short both for latency and retention) with respect to the long-time memory (like NAND, long both for latency and retention), thus contributing to the heterogeneous memory eco-system. In particular, hints on embedded PCM are considered, while more extensive discussion is reserved for PCM in the storage class memory arena and in the neuromorphic and in-memory computing applications.

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WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory

et al. 2022

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Phase-change memory (PCM) is a promising non-volatile memory device due to its attractive properties such as fast access time and byte-addressability. However, PCM is still difficult to be used as a main memory because of its weakness in endurance and write disturbance. Conventional wearleveling algorithms have attempted to handle short endurance, but they have not addressed the issue of write disturbance even though both issues are caused by write operations to PCM. This paper proposes a wear-leveling algorithm that addresses not only the endurance, but also the write disturbance. From the observation that the write disturbance errors and short endurance issues mostly take place in hot addresses, the proposed algorithm first detects hot addresses and maps them to 'hot' regions, which are customized memory regions designed to be robust to write disturbance errors and to support effective wear-leveling. The 'hot' region is not fixed to a specific part, but it moves over an entire memory space to make every cell belong to 'hot' regions in a uniform manner. On the other hand, cold addresses are mapped in 'normal' memory regions by simple linear mapping to reduce the hardware overhead. The proposed algorithm can reduce the write disturbance errors by more than 70% with only a slight instruction per cycle (IPC) degradation. Moreover, the wear-leveling performance is also enhanced by more than 3% compared to other wear-leveling algorithms.

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Hybrid SSD with PCM

Cited by 5 publications

References 1 publication

Phase Change and Magnetic Memories for Solid-State Drive Applications

Phase Change and Magnetic Memories for Solid-State Drive Applications

Phase change memory applications: the history, the present and the future

WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory

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