Hybrid timing-address oriented load-store queue filtering for an x86 architecture

Apolloni, Rubén; Chaver, Daniel; Castro, Fernando; Piñuel, Luis; Prieto, Manuel; Tirado, Francisco

doi:10.1049/iet-cdt.2010.0004

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2014

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“…To accomplish this task, a load-store queue (LSQ) is used to detect and forward or recover the data [7] [8]. Therefore, aggressive scheduling can be used with this technique, which involves hardware overhead.…”

Section: Introductionmentioning

confidence: 99%

Simulation-based memory dependence checker for CGRA-mapped code verification

Shim

Ryu

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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In a coarse-grained reconfigurable array (CGRA) architecture, software pipelining is primarily used to improve performance by exploiting loop-level parallelism (LLP). In this technique, the loop-carried memory dependence in user code prevents high parallelism, and it is difficult to be detected. In this paper, we propose a simulation-based memory dependence checker, which is used in the verification of CGRA-mapped code. We use as a reference the memory access behavior of the sequential processor and compare it to that of the CGRAmapped code. Although it cannot guarantee perfect verification of memory dependence violations, our approach is useful by guiding the programmer to modify the source code. When a memory dependence violation is detected, our approach provides debugging information from the sequential compiled code. Moreover, our checker is implemented in the register transfer level; it enables verification time reduction and the testing of the CGRA-mapped code with a large test input stream in FPGA or ASIC implementations.

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Section: Introductionmentioning

confidence: 99%