Hydroxyl-free buffered dielectric for graphene field-effect transistors

Jin, Zhi; Ma, P.; Wang, Shaoqing; Peng, Songang; Zhang, Dayong; Shi, Jingyuan; Niu, Jiebin; Yu, Guanghui; Wang, Xuanyun; Li, Mei

doi:10.1016/j.carbon.2015.01.030

Cited by 5 publications

(4 citation statements)

References 51 publications

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“…Figure a shows the Raman results from different technological processes of the graphene device, including as-patterned, with PS film and PS dissolving processes. The G and 2D bands of the pristine graphene corresponding to the peak centered at ∼1585 and ∼2700 cm –1 have been reported previously. − The absence of any D-band at ∼1350 cm –1 indicates that the graphene maintained a defect-free layer of sp 2 -hybridized carbon after a series of technological processes. − The presence of the enlarged G and 2D bands (Figure b) sharply blue-shifted 7 and 10 cm –1 , respectively, compared to the pristine graphene, indicating that a transferred process assisted by PMMA leaves the residue on the graphene surface. Blue-shifted Raman bands are attributed to the hole doping in graphene .…”

Section: Resultssupporting

confidence: 67%

Achieving Low Contact Resistance by Engineering a Metal–Graphene Interface Simply with Optical Lithography

Kong

Wang

Xia

et al. 2017

ACS Appl. Mater. Interfaces

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High-performance graphene-based transistors crucially depend on the creation of the high-quality graphene-metal contacts. Here we report an approach for achieving ultralow contact resistance simply with optical lithography by engineering a metal-graphene interface. Note that a significant improvement with optical lithography for the contact-treated graphene device leads to a contact resistance as low as 150 Ω·μm. The residue-free sacrificial film impedes the photoresist from further doping graphene, and all of the source and drain contact regions defined by optical lithography remain intact. This approach, being compatible with complementary metal-oxide-semiconductor (CMOS) fabrication processes regardless of the source of graphene, would hold promise for the large-scale production of graphene-based transistors with optical lithography.

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Section: Resultssupporting

confidence: 67%

Achieving Low Contact Resistance by Engineering a Metal–Graphene Interface Simply with Optical Lithography

Kong

Wang

Xia

et al. 2017

ACS Appl. Mater. Interfaces

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“…Particularly, this parameter establishes the performance that, for example, graphene-based field-effect transistors (GFETs) will achieve [25]. In addition, configurations such as those based on top gate (TG) and where materials for oxide with high dielectric constants (k) are used onto or under graphene [17,[26][27][28][29], configurations with suspended graphene [23,28,[30][31][32] or substrate-less graphene, or at encapsulating (embedding) graphene in dielectric materials, such as boron nitride, with lattice matched [28,[33][34][35], have maximal mobility. When graphene is embedded in dielectric materials, the strong Coulomb scattering increases the electrical mobility [28].…”

Section: Electrical Properties Of the Graphene And Basic Devicesmentioning

confidence: 99%

State-of-the-Art Electronic Devices Based on Graphene

Vargas-Bernal¹

2016

Nanoelectronics and Materials Development

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Graphene can be considered as the material used for electronic devices of this century, due to its excellent physical and chemical properties, which have been studied and implemented from a theoretical basis and have allowed the development of unique and innovative applications. The need for an ongoing study of the state-of-the-art electronic devices is ultimately useful for the progress achieved so far and future project applications. To date, graphene has been used individually in composite, hybrid materials or functional materials. In this chapter, an overview of their applications in nanoelectronics, particularly with an emphasis directed to flexible electronics, is presented. The description of the advantages and properties of graphene at a level of materials science and engineering is presented, in order to spread its enormous potential. In addition, the future prospects of these applications arising from the developments made currently in the laboratory phase are examined.

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“…Meanwhile, there are few related studies, and the stability of the conditions needs to be further explored [16]. In addition, various kinds of polymers have been used as ALD seed layers, such as NFC [7], PTCDA [17], and BCB [18]. However, the polymer layers tend to be thicker and have lower dielectric constants, which can significantly reduce the gate capacitance and control capability.…”

Section: Introductionmentioning

confidence: 99%

Seeding-Layer-Free Deposition of High-k Dielectric on CVD Graphene for Enhanced Gate Control Ability

et al. 2022

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The gate insulator is one of the most crucial factors determining the performance of a graphene field effect transistor (GFET). Good electrostatic control of the conduction channel by gate voltage requires thin gate oxides. Due to the lack of the dangling bond, a seed layer is usually needed for the gate dielectric film grown by the atomic layer deposition (ALD) process. The seed layer leads to the high-quality deposition of dielectric films, but it may lead to a great increase in the thickness of the final dielectric film. To address this problem, this paper proposes an improved process, where the self-oxidized Al2O3 seed layer was removed by etching solutions before atomic layer deposition, and the Al2O3 residue would provide nucleation sites on the graphene surface. Benefiting from the decreased thickness of the dielectric film, the transconductance of the GFET using this method as a top-gate dielectric film deposition process shows an average 44.7% increase compared with the GFETs using the standard Al evaporation seed layer methods.

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Hydroxyl-free buffered dielectric for graphene field-effect transistors

Cited by 5 publications

References 51 publications

Achieving Low Contact Resistance by Engineering a Metal–Graphene Interface Simply with Optical Lithography

Achieving Low Contact Resistance by Engineering a Metal–Graphene Interface Simply with Optical Lithography

State-of-the-Art Electronic Devices Based on Graphene

Seeding-Layer-Free Deposition of High-k Dielectric on CVD Graphene for Enhanced Gate Control Ability

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