Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation

Chen, Hui; Cheng, Kaifeng; Lu, Zhonghai; Fu, Yuxiang; Li, Li

doi:10.1109/tcsii.2020.2971974

Cited by 16 publications

(10 citation statements)

References 20 publications

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“…rp2 [3] rp1 [3] rp2 [4] rp1 [4] rp2 [5] rp1 [5] rp2 [6] Full Adder Full Adder Full Adder pp3 [9] ~pp2 [11] ~pp1 [11] bq [8] pp4 [7] Full Adder Half Adder Full Adder pp4 [8] pp3 [10] bq [9] 1'b1 bq [10] Full Adder pp4 [9] ~pp3 [11] Full Adder … … … rp1 [11] rp2 [12] rp1 [12] rp2 [13] rp1 […”

Section: Half Addermentioning

confidence: 99%

“…rp2 [3] rp1 [3] rp2 [4] rp1 [4] rp2 [5] Full Adder Full Adder pp3 [9] ~pp2 [11] ~pp1 [11] bq [8] Full Adder…”

Section: Half Addermentioning

confidence: 99%

“…Approximation methods are also further classified into two types: PWL approximation and high-degree polynomial approximation (HPA). Among the above methods, CORDIC can be used to implement only some of the complex functions of interest, such as logarithmic and exponential functions [5][6][7][8][9]. The other methods are universally applicable to various complex functions.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

Zheng

Zhao²,

Wang³

et al. 2022

Electronics

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In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction evaluation based on an optimized piecewise linear (PWL) method. The proposed segmentor automatically divides nonlinear functions into the fewest segments with a predefined maximum absolute error (MAE) and fractional bit width of the slope. In addition, a multiplier was optimized via Booth encoding to reduce the number of rows in the partial product matrix. Compressors were used to shorten the critical path. The results of application-specific integrated circuit (ASIC) implementation reveal that all metrics of the proposed architecture are improved for single functions, without any compromise. Moreover, reconfigurable technology was introduced for implementing multiple functions while reusing computing resources. Compared to a corresponding architecture without reuse, the area and power of this reconfigurable architecture are reduced by 37.48% and 45.60%, respectively, at the same frequency.

show abstract

Section: Half Addermentioning

confidence: 99%

“…rp2 [3] rp1 [3] rp2 [4] rp1 [4] rp2 [5] Full Adder Full Adder pp3 [9] ~pp2 [11] ~pp1 [11] bq [8] Full Adder…”

Section: Half Addermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

Zheng

Zhao²,

Wang³

et al. 2022

Electronics

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show abstract

“…Ref. [14] proposed a single-precision floating-point THV-CORDIC algorithm that employs a pipelined structure for computing the base-2 logarithm and allows for configurable iteration counts, balancing precision and area as needed. Ref.…”

Section: Introductionmentioning

confidence: 99%

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

Chang,

Wang

2023

Electronics

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With the rapid development of technologies like artificial intelligence, high-performance computing chips are playing an increasingly vital role. The inverse hyperbolic sine and inverse hyperbolic cosine functions are of utmost importance in fields such as image blur and robot joint control. Therefore, there is an urgent need for research into high-precision, high-performance hardware Intellectual Property (IP) for arcsinh and arccosh functions. To address this issue, this paper introduces a novel 128-bit low-latency floating-point hardware IP for arcsinh and arccosh functions, employing an enhanced Coordinate Rotation Digital Computer (CORDIC) algorithm, achieving a computation precision of 113 bits in just 32 computation cycles. This significantly enhances computational efficiency while reducing hardware implementation latency. The results indicate that, when compared to Python standard results, the calculated error of the proposed hardware IP does not exceed 8×10−34. Furthermore, this paper synthesizes the completed IP using the TSMC 65 nm process, with a total IP area of 2.1056 mm2. Operating at a frequency of 300 MHz, its power is 22.4 mW. Finally, hardware implementation and resource analysis are conducted and compared on an Field Programmable Gate Array (FPGA). The results show that the improved algorithm trades a slight area increase for lower latency and higher accuracy. The designed hardware IP is expected to provide a more accurate and efficient computational tool for applications like image processing, thereby advancing technological development.

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“…The CORDIC algorithm was first proposed in 1959 by E. Volder for computing trigonometric functions, multiplication and division [11,12]. To expand the usage areas, the CORDIC algorithm is applied in the computation of logarithms, exponentials, square roots, arbitrary Nth root, complex operations [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. In the implementation of the CORDIC algorithm, the type of computation (addition or subtraction) in the iteration is determined by the rotation direction.…”

Section: Introductionmentioning

confidence: 99%

An optimized hardware implementation of the CORDIC algorithm

Lyu

Wang

et al. 2022

IEICE Electron. Express

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In this paper, we propose a software-based simulator and an optimized hardware implementation of the CORDIC algorithm. The number of iterations and the bit width are selected by their relationship calculated by the simulator to satisfy precision requirement. In the proposed hardware implementation, the addition and subtraction operations share the hardware resources. The two's complement is calculated in two steps: inverting and adding one. The adding one operation is integrated in the addition component of the iteration. In addition, a 3:2 compressor is used to reduce the number of adders, and a carry look-ahead adder is used to reduce the critical path. The synthesized results show that when compared with state-of-the-art designs, our method reduces the area by 53.79% and the delay by 58.97% while maintaining the same precision.

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Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation

Cited by 16 publications

References 20 publications

Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

Design of Hardware IP for 128-Bit Low-Latency Arcsinh and Arccosh Functions

An optimized hardware implementation of the CORDIC algorithm

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