HyperTransport 3 Core: A Next Generation Host Interface with Extremely High Bandwidth

Kalisch, Benjamin; Giese, Alexander; Litz, Heiner; Brüning, Ulrich

doi:10.11588/heidok.00009113

2009

DOI: 10.11588/heidok.00009113

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HyperTransport 3 Core: A Next Generation Host Interface with Extremely High Bandwidth

Benjamin Kalisch

Alexander Giese²,

Heiner Litz³

et al.

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Cited by 2 publications

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An FPGA based verification platform for HyperTransport 3.x

Litz

Fröning

Thurmer

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

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In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interconnect which is particularly used in AMDs novel Opteron processor series. As it is an open protocol, a broad application range exists ranging from southbridge chips over closely coupled accelerators to add in cards. Its main advantage over PCI-Express is that it allows direct connection to the CPU resulting in significantly improved latency performance. To enable the development of new HyperTransport products we herein present the very first FPGA based prototyping platform for HT3.x. Such a platform is enormously valuable as new designs can be tested in real world systems before producing an costly application specific integrated circuit (ASIC). Due to the high operating frequencies of HT3.x an FPGA based solution is extremely challenging as we will describe in this paper. Our presented architecture is evaluated and implemented in the form of a printed circuit board (PCB). This add-in card represents the world's first available HyperTransport 3 device. Early adopters of HT3 benefit from the results of this work for rapid prototyping and Hardware/Software coverification of new HT3 designs and products.

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An FPGA based verification platform for HyperTransport 3.x

Litz

Fröning

Thurmer

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

Self Cite

View full text Add to dashboard Cite

show abstract

A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing

Lemke¹,

Kapferer²,

Giese³

et al. 2011

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HyperTransport 3 Core: A Next Generation Host Interface with Extremely High Bandwidth

Cited by 2 publications

References 4 publications

An FPGA based verification platform for HyperTransport 3.x

An FPGA based verification platform for HyperTransport 3.x

A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing

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