Hysteresis analysis in excimer‐laser‐annealed low‐temperature polycrystalline‐silicon thin‐film transistors

In this work, we report that H in poly-Si and surface potential in channel play a critical role in the performance and stability of LTPS TFTs. We increased H contents in poly-Si film from 0.059 to 0.061 atom% resulting in the decrease of the fast state trap density from 4.9~5.8 × 10 10 /cm 2 to 3.6~4.6 × 10 10 /cm 2 . Also, we increased surface potential by applying the appropriate back gate bias in TFTs, resulting in the more reduction of effective trap state density down to 1.7~2.0×10 10 /cm 2 . This resulted in the increase of the field effect mobility up to 115.4cm 2 /V·sec and decrease of hysteresis below 0.1V. We implemented these technologies into our flexible AMOLED panel.

Section: Introductionmentioning

confidence: 84%

16‐1: The role of hydrogen and surface potential in the performance and stability of poly‐Si TFTs on plastic substrates

Lee

Kim

Choi

et al. 2019

“…Recoverable image sticking is one of most important specifications inspected for mobile display, which is strongly related to hysteresis phenomenon in LTPS TFTs resulting in a threshold-voltage (Vth) shift [3][4]. In general, the main mechanism of the hysteresis phenomenon in poly-Si TFTs are reported as a trapping and detrapping process of free carriers associated with the intra-grain trap, grain-boundary trap, and interface trap between the active layer and gate insulator [5]. The protrusion height of poly-Si will impact the number of grain boundary traps, which will impact the hysteresis performance of PMOS thin film transistor (TFT) [6].…”

Section: Objective and Backgroundmentioning

confidence: 99%

48.1: Inline Low Temperature Polycrystalline Silicon Roughness and Grain Size Metrology Enabled by Electron Beam Review for a Better Process Control of Excimer Laser Annealing

Meng

Knaub

et al. 2022

In this paper, we present a brand new inline metrology solution for LTPS roughness enabled by EBR system. It was the first time that LTPS roughness inline measurement was made possible in display manufacturing industry. Moreover, a broader perspective for process monitoring was added to the existing grain size measurement function. The metrology showed the advantages of faster cycle time, non‐destructive, and extremely higher sampling rate. Several experiments were performed to show good sensitivity between roughness, grain size and ELA energy density, a‐Si thickness. The correlations between LTPS roughness, grain size and Vth shift were also demonstrated, which is very valuable for the research of PMOS hysteresis effect.

“…The hysteresis of the p-channel LTPS TFT can be explained by hole trapping and de-trapping at the interface region of the channel. There have been numerous reports to explain and trials to reduce the hysteresis by surface plasma treatment, annealing, thin active, and heating the panel, the minimum hysteresis was reported to be around 0.1V for poly-Si channel TFTs [5][6][7][8][9]. However, the research work on recovery phenomenon of the image sticking is relatively lacking, which can be attributed to the relaxation of the TFT drain current.…”

Section: Introductionmentioning

confidence: 99%

P‐12: Transient Drain Current Characteristics of Poly‐Silicon TFTs on Plastic Substrates

Li,

Qu,

Wang

et al. 2023

The mechanism and improvement of transient drain current characteristics of p‐channel low‐temperature polycrystalline silicon driving‐thin film transistor (LTPS DTFT) were studied in this work. The drain current variation with time can be simulated by attenuation of logarithmic index which might be originated from hole trapping and de‐trapping process. Simulation was used to directly correlate the transient Ids characteristics to the density of border trap. We optimized the buffer and gate insulator layer deposition condition, in addition, we applied a fixed bias in TFT bottom gate, the transient Ids decreased from 27% to 15%.