Ab-Initio Study of Neutral Indium Diffusion in Uniaxially- and Biaxially-Strained Silicon

Abstract

In this paper, we present our ab-initio study on energy configurations, minimum energy path (MEP), and migration energy for neutral indium diffusion in a uniaxial and biaxial tensile strained {100} silicon layer. Our ab-initio calculation of the electronic structure allowed us to figure out transient atomistic configurations during the indium diffusion in strained silicon. We found that the lowest-energy structure (Ins - SiTd) consists of indium sitting on a substitutional site while stabilizing a silicon self-interstitial in a nearby tetrahedral position. Our ab-initio calculation implied that the next lowest energy structure is Inj(Td), the interstitial indium at the tetrahedral position. We employed the nudged elastic band (NEB) method for estimating the MEP between the two structures. The NEB method allowed us to find that that diffusion pathway of neutral indium is kept unchanged in strained silicon while the migration energy of indium fluctuates in strained silicon.

Impact of Drift Gap, <I>N</I>-Layer, and Deep N<SUP>+</SUP> Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

“…Referring to Figure 8, we see that the proposed device has a maximum impact ionization as low as 2 44 × 10 16 cm −3 s −1 at V DS = 70 V, whereas the conventional one has a value of 6 69 × 10 19 cm −3 s −1 at the same condition, which implies that the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage. [9][10][11][12][13] Figure 9 shows the simulated device structure and the impact ionization rates at V DS = 30, 50, and 70 V. The high impact ionization spot moves from the gate to the drain due to the high level of current density. As illustrated in Figure 9, the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage.…”