I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

Souilem, Malek; Tripathi, Jai Narayan; Dghais, Wael; Hamdi, Belgacem

doi:10.1109/vlsi-soc.2019.8920351

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…The numerical analysis of (7) provides the dispersion characteristics of the fundamental passband and first stopband. It can demonstrate a low cutoff frequency.…”

Section: Analytical Methods For Estimation Of Low Cutoff Frequencymentioning

confidence: 99%

“…Considering the typical values of ρSWF, du, and fL of the MDGS-EBG structure in high-speed packages and PCBs, they are extremely small in comparison with c. Consequently, we can assume that cos(βmdu) and sin(βmdu) are approximately equal to 1 and βmdu, respectively, in the right-hand side of (7). With the aforementioned assumptions, a closed-form expression for the low cutoff frequency is derived as follows:…”

Section: Analytical Methods For Estimation Of Low Cutoff Frequencymentioning

confidence: 99%

“…Moreover, it generates noise in power delivery networks (PDNs) of high-speed integrated circuit (IC) packages and printed circuit boards (PCBs). This results in the degradation of the bit error rate performance of high-speed links [5][6][7], reduction in the on-chip timing margin of clock distribution networks [8][9][10], and electromagnetic interference (EMI) generated by radiated emission from PDNs [11][12][13][14]. The power/ground noise is induced from the resonant cavity modes of the PDNs, which can be considered as a parallel plate waveguide (PPW).…”

Section: Introductionmentioning

confidence: 99%

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Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

Kim

2022

Electronics

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In this paper, we present the impact of a meander-shaped defected ground structure (MDGS) on the slow-wave characteristics of a lowest-order passband and a low cutoff frequency of the first stopband of an electromagnetic bandgap (EBG) structure for power/ground noise suppression in high-speed integrated circuit packages and printed circuit boards (PCBs). A semi-analytical method is presented to rigorously analyze the MDGS effect. In the analytical method, a closed-form expression for a low cutoff frequency of the MDGS-EBG structure is extracted with an effective characteristic impedance and a slow-wave factor. The proposed analytical method enables the fast analysis of the MDGS-EBG structure so that it can be easily optimized. The analysis of the MDGS effect revealed that the low cutoff frequency increases up to approximately 19% while comparing weakly and strongly coupled MDGSs. It showed that the miniaturization of the MDGS-EBG structure can be achieved. It was experimentally verified that the low cutoff frequency is reduced from 2.54 GHz to 2.00 GHz by decreasing the MDGS coupling coefficient, which is associated with the miniaturization of the MDGS-EBG structure in high-speed packages and PCBs.

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“…The numerical analysis of (7) provides the dispersion characteristics of the fundamental passband and first stopband. It can demonstrate a low cutoff frequency.…”

Section: Analytical Methods For Estimation Of Low Cutoff Frequencymentioning

confidence: 99%

Section: Analytical Methods For Estimation Of Low Cutoff Frequencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

Kim

2022

Electronics

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“…Previous IO buffer-modelling methodologies, which can be classified either based on the equivalent circuit input-output buffer information specification (IBIS) or parametric curve fitting [8,9], have not clearly addressed the PVT corner simulation and its importance in the model's generation steps, worst corner identification, and in the validation of model performance. In fact, the standard multiport behavioral model structure that describes the electrical behaviors of the IO buffer circuit, while considering the PGSV variables [7][8][9], is: Since these supplies are not constant due to high-current switching through the predriver's PDN, therefore, the IBIS model fails to accurately predict the timing distortion originating from V DD , the voltage noise which affects the output eye jitter. Moreover, previous works presented an extended equivalent circuit behavioral model for SiPI simulation in the pre-driver and the driver's last stage [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

Souilem

Melício

Dghais

et al. 2022

Sensors

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This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

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Pre-driver Modeling and Jitter Estimation under Power Supply Noise

Souilem

Tripathi

Dghais

et al. 2021

2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

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I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

Cited by 4 publications

References 4 publications

Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

Pre-driver Modeling and Jitter Estimation under Power Supply Noise

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