“…In addition to above discussed related work, Adder Design [6], Thermal Aware Object Tracking on FPGA [7] and Power Optimized Memory Circuit Using HSTL IO Standard on 28nm FPGA [8] have also worked on the same parameters using some similar standards and concepts for energy efficient design [9][10][11][12]. There is 80.2%, 88.32%, 89.13% and 89.21% downgrading in IOs when we step down frequency from 100GHz to 10GHz, 1GHz, 0.1GHz, 0.01GHz respectively.…”