IBIS model generation and validation of CMOS Buffer

Divya, K.; Elechithaya, Vishwanath; Padmini, T N

doi:10.1109/vitecon.2019.8899411

2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN) 2019

DOI: 10.1109/vitecon.2019.8899411

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IBIS model generation and validation of CMOS Buffer

K. Divya

Vishwanath Elechithaya

T N Padmini

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2023

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Cited by 2 publications

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Ibis Model Output Impedance Correction Approach Using CCCS

Vardanyan¹

2023

Proceedings

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With the CMOS technology size scaling aggressively and the transmitter (TX) outp¬u¬t resistance becoming smaller and smaller, it becomes necessary to have a good impedance correlation between TX and receiver (RX). The mismatch between the impedances can cause a noise and a response which will dramatically decrease the efficiency of the circuit. Nowadays, those mismatches are being tested using IBIS (Input/output Buffer Information Specification) models owing to low cost and testing speed. A method is proposed to use a current-controlled current source (CCCS) which will decrease the mismatch and make it less than 1%. The proposed method can be implemented for all types of TX drivers and IBIS models.

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Ibis Model Output Impedance Correction Approach Using CCCS

Vardanyan¹

2023

Proceedings

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Ibis Model Accuracy Improvement Using Variable Step

GHUKASYAN,

VARDANYAN,

PAPYAN

et al. 2023

Proceedings

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In all times of integrated circuits (IC) manufacturing, the speed of getting the product on the market has been the main problem for all manufacturers. The main reason for late products has always been the speed of the tools that carry out the testing. The main simulator used by every manufacturer is the SPICE simulator, but with the SPICE simulator it can take up to months to simulate the whole TXRX macro. But since the 1990s with the introduction of the I/O Buffer Information Specification (IBIS) models, the testing time has decreased dramatically. A method is proposed to generate IBIS models with a variable step, that will help to increase the accuracy of the IBIS model during signal integrity (SI) simulations and will correlate with SPICE simulations better. The proposed method can be implemented for all types of TX drivers and IBIS models.

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IBIS model generation and validation of CMOS Buffer

Cited by 2 publications

References 8 publications

Ibis Model Output Impedance Correction Approach Using CCCS

Ibis Model Output Impedance Correction Approach Using CCCS

Ibis Model Accuracy Improvement Using Variable Step

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