iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

Abstract

Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efficient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dualfunction links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques.

CHIPPER: A low-complexity bufferless deflection router

“…Reducing cost and complexity in buffered routers: Elastic Buffer Flow Control [35] makes use of the buffer space inherent in pipelined channels to reduce buffer cost. The iDEAL router [26] reduces buffering by using dual-function links that can act as buffer space when necessary. The ViChaR router [39] dynamically sizes VCs to make more efficient use of a buffer budget, allowing reduced buffer space for equivalent performance.…”

“…In particular, one line of recent work has investigated how to eliminate in-router buffers altogether [38,19,16], or minimize them with alternative designs [25,26,39]. The completely bufferless designs either drop [19,16] or misroute (deflect) [38] flits when contention occurs.…”

Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks

“…Instead, our goal is to adjust the circuit parameters to avoid these failures in the NoC. To enhance the energy efficiency and reduce the buffering requirements in an NoC, Kodi et al advocate multi-purposing repeater logic on links as storage elements [25].…”

Smart Multicrossbar Router Design in NOC

“…Initially iDEAL, a low-power area-efficient NoC ia achive by reducing the number of buffers within the router [9]. Other designs targeting power saving with router design have different approaches.…”