IEEE 1588 Transparent Clock architecture for FPGA-based network devices

Moreira, Naiara; Astarloa, Armando; Lázaro, Jesús; Garcia, Alain; Ormaetxea, Enekoitz

doi:10.1109/isie.2013.6563777

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…Recently, the topic of synchronization in network nodes has attracted significant attention for a number of applications [1][2][3][4][5][6][7][8][9][10]. In many cases the global positioning system (GPS) is used to synchronize frequency and time accuracy in the sub-microsecond range.…”

Section: Introductionmentioning

confidence: 99%

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Levy

Pinchas

2015

Mathematical Problems in Engineering

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To support system-wide synchronization accuracy and precision in the sub-microsecond range without using GPS technique, the precise time protocol (PTP) standard IEEE-1588 v2 is chosen. Recently, a new clock skew estimation technique was proposed for the slave based on a dual slave clock method that assumes that the packet delay variation (PDV) in the Ethernet network is a constant delay. However, papers dealing with the Ethernet network have shown that this PDV is a long range dependency (LRD) process which may be modeled as a fractional Gaussian noise (fGn) with Hurst exponent (H) in the range of0.5<H<1. In this paper, we propose a new clock skew estimator based on the maximum likelihood (ML) technique and derive an approximated expression for the Cramer-Rao lower bound (CRLB) both valid for the case where the PDV is modeled as fGn (0.5<H<1). Simulation results indicate that our new clock skew method outperforms the dual slave clock approach and that the simulated mean square error (MSE) obtained by our new proposed clock skew estimator approaches asymptotically the developed CRLB.

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Section: Introductionmentioning

confidence: 99%

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Levy

Pinchas

2015

Mathematical Problems in Engineering

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“…An IEEE 1588 auxiliary timestamp with dynamic frequency compensation is also proposed; it is designed as a chip to reduce the delay of protocol stacking and to improve the accuracy of time so that it can be applied to more needs. Based on the FPGA-based IEEE 1588 standard synchronization architecture [17], we implemented a timestamp that can be captured between the PHY layer and the MAC layer, eliminating delay jitter caused by network protocol stacking, and thereby improving synchronization accuracy. When the Primary and Secondary are connected through a network cable, the deviation of IEEE 1588 clock synchronization can be limited to ±20 ns.…”

Section: Itemmentioning

confidence: 99%

Development Board Implementation and Chip Design of IEEE 1588 Clock Synchronization System Applied to Computer Networking

et al. 2023

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With the vigorous development of industrial automation and the Internet of things, the transmission of data is more dependent on immediacy, so network devices have higher and higher requirements for time synchronization accuracy. The clock source of common network devices is provided by the transistor oscillator in the server, but the oscillator will change with factors such as aging and temperature, and it cannot be guaranteed that the oscillator in the server will work at the same frequency. Time synchronization can be achieved by technologies such as IRIG-B, NTP, or IEEE 1588 (PTP), but the hardware cost of building IRIG-B is high, and NTP has the lowest cost, but it can only provide time accuracy from milliseconds to microseconds. PTP can provide sub-microsecond or even nanosecond time precision. It is a system of time synchronization mechanisms through Ethernet transmission. In this article, we first propose a time synchronization system using the development board and PDP protocol. On the Xilinx Zynq-7000 SOC platform of Petalinux, we implement the hardware solution of Linux PTP. The hardware time stamp is 20 ns. To improve the accuracy, the congenital frequency error between the oscillators must be considered. Therefore, a PTP auxiliary time stamp with dynamic frequency compensation is proposed and designed into a chip. Experimental results show that at 45 nm (TN40G) it can operate at 370 MHz and achieve 2.7 ns resolution, which can be applied to more demands.

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“…REVERSEPTP delivers the accuracy just like conventional synchronization protocols. [96] Major contribution is a new TC architecture for a FPGAbased network device.…”

Section: Evaluated Performance In a Test Bed With 34 Nodesmentioning

confidence: 99%

IEEE 1588 for Clock Synchronization in Industrial IoT and Related Applications: A Review on Contributing Technologies, Protocols and Enhancement Methodologies

et al. 2020

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Precise time synchronization becomes a vital constituent due to the rigorous needs of several time-sensitive applications. The clock synchronization protocol is one of the fundamental factors that can define the quality of communication. Our study starts with a brief discussion on the application domain of precise time synchronization and comes with an in-depth study of the synchronization with the main focus on the IEEE 1588 Precision Time Protocol (PTP). We have compared the well-known synchronization techniques and conclude that the PTP is the most appropriate answer to robust clock synchronization though challenges are there that requires thoughtful efforts and modification in the current version. The working mechanism and main components of the PTP network are discussed. We have established a testbench using commercially available devices and development boards to evaluate the PTP performance under different configurations. Major sources of synchronization error and other aspects contributing to precision are examined. This paper discussed numerous approaches that could enhance the performance of the PTP protocol. Structures for PTP based wireless clock synchronization required by advanced applications has also been discussed. In the end, paper focuses on the main industrial application areas in which PTP plays an important role, including WLAN, optical data centers, Smart grid, IEC 61850, etc. We conclude the paper by identifying the future trends and research directions for PTP based clock synchronization.

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IEEE 1588 Transparent Clock architecture for FPGA-based network devices

Cited by 15 publications

References 6 publications

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Development Board Implementation and Chip Design of IEEE 1588 Clock Synchronization System Applied to Computer Networking

IEEE 1588 for Clock Synchronization in Industrial IoT and Related Applications: A Review on Contributing Technologies, Protocols and Enhancement Methodologies

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