IEEE-Compliant IDCT on FPGA-Augmented TriMedia

Abstract

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Keywords: configurable computing, VLIW processor, field-programmable gate array, inverse discrete cosine transform 196 Sima et al.

Eclipse : Flexible Media Processing in a Heterogeneous Multiprocessor Template

“…to transport and synchronize data access) becomes relatively large. Therefore, fine-grain hardware acceleration is sometimes embedded in RISC [9] or VLIW cores [133] in the form of complex function units. The Molen project [144][133] worked this concept out for MPEG encoding/decoding functions.…”

“…Therefore, a DCT coprocessor can use the same data path for the implementation of inverse and forward DCT. Moreover, implementing dedicated multipliers with fixed constants provides high throughput at minimal hardware cost [86] [133]. The internal state of this coprocessor is void after processing a DCT block.…”