IEEE Standard for Floating-Point Arithmetic

Zuras, D.; Cowlishaw, M. F.; Aiken, Alex; Applegate, Matthew; Bailey, David H.; Bass, Steve; Bhandarkar, Dileep; Bhat, M.; Bindel, David; Boldo, Sylvie; Canon, Stephen; Carlough, S.R.; Cornea, Marius; Crawford, John H.; Darcy, Joseph D.; Sarma, Debjit Das; Daumas, Marc; Davis, Bob; Davis, Mark S.; Delp, Dick; Demmel, J.; Erle, M.A.; Fahmy, Hossam A. H.; Fasano, J. P.; Fateman, Richard J.; Feng, E. J.; Ferguson, W. S.; Fit-Florea, A.; Fournier, Laurent Sébastien; Freitag, Chip; Godard, Ivan; Golliver, Roger A.; Gustafson, David A.; Hack, Michel; Harrison, John; Hauser, John R.; Hida, Yozo; Hinds, C.N.; Hoare, Graydon; Hough, David; Huck, Jerry; Hull, Jim; Ingrassia, Michael; James, David V.; James, Rick; Kahan, W.; Kapernick, J. S.; Karpinski, Richard; Kidder, Jeff; Koev, Plamen; Li, Ren-Cang; Liu, Zhishun A.; Mak, Raymond H.; Markstein, Peter; Matula, David W.; Melquiond, Guillaume; Mori, Nobuyoshi; Morin, Ricardo; Nedialkov, Ned; Nelson, Craig E.; Oberman, Stuart F.; Okada, Jon; Ollmann, Ian R.; Parks, Michael L.; Pittman, Tom; Postpischil, Eric; Riedy, Jason; Schwarz, E.; Scott, David W.; Senzig, D. N.; Sharapov, Ilya; Shearer, J; Siu, Kin Wai Michael; Smith, Ron; Stevens, C.A.; Tang, Pushan; Taylor, Pamela J.; Thomas, James W.; Thompson, Brandon J.; Thrash, Wendy; Toda, Neil; Trong, Son Dao; Tsai, Leonard; Tsen, Charles; Tydeman, Fred; Wang, Liang K.; Westbrook, Scott; Winkler, Steve; Wood, Anthony; Yalçinalp, Ümit; Zemke, Fred; Zimmermann, Paul

doi:10.1109/ieeestd.2008.4610935

Cited by 398 publications

(223 citation statements)

References 11 publications

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“…The key space is configured by the four numbers x(i), y(i), and z(i), and L. With number of about 16 decimal digits precision [30] the key space is more than 2 172 . This is large enough against exhaustive attack methods [1].…”

Section: B Key Spacementioning

confidence: 99%

Least Significant Bit Steganography using Hitzl-Zele Chaotic Map

Kordov

Stoyanov

2017

International Journal of Electronics and Telecommunications

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Abstract-We propose a novel least significant bit steganography algorithm based on a Hitzl-Zele chaotic function. On the first step a pseudorandom generator is constructed for chaotic pixel selection for hiding the secret message. Exact study has been provided on the novel scheme using visual inspection, peak signal-to-noise ratio, and histogram analysis. The experimental data show excellent performance of the novel stego technique.

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Section: B Key Spacementioning

confidence: 99%

Least Significant Bit Steganography using Hitzl-Zele Chaotic Map

Kordov

Stoyanov

2017

International Journal of Electronics and Telecommunications

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“…The IEEE-754 standard [1] defines an expected behavior of FP computations. It describes binary and decimal formats to represent FP numbers, and specifies the elementary operations and the comparison operators on FP numbers.…”

Section: The Ieee-754 Standard For Floating-point Arithmeticmentioning

confidence: 99%

Multi-Prover Verification of Floating-Point Programs

Ayad

Marché

2010

Automated Reasoning

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Abstract. In the context of deductive program verification, supporting floatingpoint computations is tricky. We propose an expressive language to formally specify behavioral properties of such programs. We give a first-order axiomatization of floating-point operations which allows to reduce verification to checking the validity of logic formulas, in a suitable form for a large class of provers including SMT solvers and interactive proof assistants. Experiments using the Frama-C platform for static analysis of C code are presented.

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“…As shown in Figure 4.1, the format closely resembles IEEE-754 single precision [IEEE, 2008], but uses 32 bits for the significand rather than 23. In this configuration, integer arithmetic is based on 32-bit two's complement notation.…”

Section: Number Representationmentioning

confidence: 99%

“…Many manufacturers and researchers label their work as IEEE compliant while in fact they just implement a subset of the functionality defined in [IEEE, 2008]. We would therefore not call Sabrewing IEEE compliant, but it does produce IEEE compliant results.…”

Section: Ieee Compliancementioning

confidence: 99%

Versatile architectures for onboard payload signal processing

Walters¹

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This thesis describes a system-on-chip (SoC) architecture for future space missions. The SoC market for deep-space missions develops slowly and is limited in features compared to the market of consumer electronics. Where consumers often cannot keep up with the features which are offered to them and sometimes even question the need for some of the options that electronics offer them, computer architectures for deep-space missions should fulfill different needs. Space is a harsh environment which requires SoCs to be shielded from radiation by hardening techniques. The missions often have a very long life-cycle: it can take more than fifteen years from the early planning stages to decommissioning of a satellite platform. The harsh environment, long lifetime and no possibility to change the hardware after launch together with the fact that mass and energy are constrained make architecture development for space more challenging than for consumer electronics.The need for a new SoC for on-board payload processing is high. The reason is mainly due to the increased quantity of data from sensors. More sensors are mounted on board of satellites and the sensors themselves produce larger volumes of data. The bandwidth, however, to send this data back to Earth is limited. To cope with the increase in data and limitation of bandwidth, the satellite platforms need to have more processing power for distilling the information from the sensor data and compress this information sufficiently. Information distillation and compression are driving forces for algorithm development and these algorithms need to run on on-board processing platforms. Of course, algorithm development and platform development are related: algorithm development pushes platform development further while limitations of the platforms often hold back the capabilities of algorithms. This relation is explored in this thesis and from this, requirements in terms of processing power, scalability and power consumption are derived to develop a payload processing platform.One topic of discussion related to processing platforms is often the need for hardware floating-point. This discussion is more prevalent for on-board payload processing where architecture developers want to keep the processing platform as lean as possible. Arguments in favor of small area, low power and low design complexity normally prevent inclusion of floating-point hardware i in space platforms. To overcome these arguments, part of the research reported in this thesis has focused on a light-weight floating point unit.Another difficulty for European missions is the fact that most architectures are developed based around technology from the United States of America. The USA, however, has very strict export regulations regarding technology that potentially could be used for military purposes. Although the research done by the European Space Agency is strictly for civilian purposes, this needs to be proven each time that technology from the USA is procured.This thesis presents a hardware fused-mu...

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IEEE Standard for Floating-Point Arithmetic

Cited by 398 publications

References 11 publications

Least Significant Bit Steganography using Hitzl-Zele Chaotic Map

Least Significant Bit Steganography using Hitzl-Zele Chaotic Map

Multi-Prover Verification of Floating-Point Programs

Versatile architectures for onboard payload signal processing

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