IEEE 5th Workshop on Signal Processing Advances in Wireless Communications, 2004.
DOI: 10.1109/spawc.2004.1439315
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IFFT/FFTcore architecture with an identical stage structure for wireless LAN communications

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Cited by 3 publications
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“…Figure 2 and Figure 3 show the HiperLAN/2 physical layer transceiver chain designed according to the HiperLAN/2 standard [1] [3]. We have explored and implemented new hardware architectures [6][7][8] [9] to improve some complex algorithms in the HiperLAN/2 chain, obtaining synthesizable models for the digital part of the physical layer of both the HiperLAN/2 transmitter and receiver validated in the hardware architecture. In particular, we have designed mode three with a 12Mbits/s data transmission rate.…”
Section: Developed Modelsmentioning
confidence: 99%
“…Figure 2 and Figure 3 show the HiperLAN/2 physical layer transceiver chain designed according to the HiperLAN/2 standard [1] [3]. We have explored and implemented new hardware architectures [6][7][8] [9] to improve some complex algorithms in the HiperLAN/2 chain, obtaining synthesizable models for the digital part of the physical layer of both the HiperLAN/2 transmitter and receiver validated in the hardware architecture. In particular, we have designed mode three with a 12Mbits/s data transmission rate.…”
Section: Developed Modelsmentioning
confidence: 99%
“…Table 1 summarizes the features of some FFT/IFFT processors for OFDM systems proposed in the literature. Proposals such as (Chang & Park, 2004;Serrá et al, 2004) employed a monoprocessor architecture to process the FFT. (Jiang et al, 2004;Lin, Liu & Lee, 2004) used parallel architectures and (Kuo et al, 2003) chose a cached memory monoprocessor architecture for the FFT processing in an OFDM system.…”
Section: Introductionmentioning
confidence: 99%
“…• For the monoprocessor architectures, radix 2 (Serrá et al, 2004) and radix 4 (Chang & Park, 2004) algorithms have been used. (Jung et al, 2005) 64 Pipeline-MDC r-2 DIT WLAN (Maharatna et al, 2004) 64 Pipeline r-2 DIT WLAN (Serrá et al, 2004) 64 Monoprocessor r-2 DIT WLAN (Lin et al, 2005) 128 Pipeline-MRMDF MR 2/2 3 DIF UWB (Saberinia, 2006) 128 Pipeline-BRMDC r-2 DIF UWB (Lee et al, 2006) 128 Pipeline-SDF r-2 4 DIF UWB (Liu et al, 2007) 64/128 Pipeline 8-path DF MR DIF UWB (Cortés et al, 2007) 128 Pipeline r-2 4 DIF UWB (Bidet et al, 1995) 8192 Pipeline-SDC r-4/2 DIF DVB-T (Lin, Liu & Lee, 2004) 8192 Parallel r-2 3 DIT DVB-T (Wang et al, 2005) 2/8 K Pipeline-SDF r-4/2 DIF DVB-T ( Lenart & Owal, 2006) 2/4/8 K Pipeline-SDF r-2 2 DIF DVB-T/H (Lee & Park, 2007) 8K Pipeline-SDF BD DVB-T (He & Torkelson, 1998) 1024 Pipeline-SDF r-2 2 DIF OFDM (Kuo et al, 2003) 64-2048 Cached memory r-2 DIT OFDM (Chang & Park, 2004) 1024 Monoprocessor r-4 DIF OFDM (Jiang et al, 2004) 64 Parallel r-2 DIT OFDM (Lin, Lin, Chen & Chang, 2004) 64 Pipeline r-2 DIF MIMO (Rudagi et al, 2010) 64 Pipeline r-2 DIT OFDM (Yu et al, 2011) 64 Pipeline r-2 DIF OFDM (Tsai et al, 2011) 64 Pipeline MR OFDM (Turrillas et al, 2010) 32 K Pipeline r-2 k DIF DVB-T2 Table 1.…”
Section: Introductionmentioning
confidence: 99%
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