iGPU: Exception support and speculative execution on GPUs

Menon, Jai; Kruijf, Marc de; Sankaralingam, Karthikeyan

doi:10.1109/isca.2012.6237007

Cited by 23 publications

(36 citation statements)

References 35 publications

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“…Table 1 classifies prior work in terms of its application domain and the level at which idempotence is used and identified [2,9,10,12,16,19,21,23,25,31,36]. One of the earliest uses is by Mahlke et al in using restartable instruction sequences for exception recovery in speculative processors [23].…”

Section: Introductionmentioning

confidence: 99%

Static analysis and compiler design for idempotent processing

Kruijf

Sankaralingam

Jha

2012

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation

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Recovery functionality has many applications in computing systems, from speculation recovery in modern microprocessors to fault recovery in high-reliability systems. Modern systems commonly recover using checkpoints. However, checkpoints introduce overheads, add complexity, and often save more state than necessary.This paper develops a novel compiler technique to recover program state without the overheads of explicit checkpoints. The technique breaks programs into idempotent regions-regions that can be freely re-executed-which allows recovery without checkpointed state. Leveraging the property of idempotence, recovery can be obtained by simple re-execution. We develop static analysis techniques to construct these regions and demonstrate low overheads and large region sizes for an LLVM-based implementation. Across a set of diverse benchmark suites, we construct idempotent regions close in size to those that could be obtained with perfect runtime information. Although the resulting code runs more slowly, typical performance overheads are in the range of just 2-12%.The paradigm of executing entire programs as a series of idempotent regions we call idempotent processing, and it has many applications in computer systems. As a concrete example, we demonstrate it applied to the problem of compiler-automated hardware fault recovery. In comparison to two other state-of-the-art techniques, redundant execution and checkpoint-logging, our idempotent processing technique outperforms both by over 15%.

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Section: Introductionmentioning

confidence: 99%

Static analysis and compiler design for idempotent processing

Kruijf

Sankaralingam

Jha

2012

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation

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“…They do not support exceptions or interruptions, which prevents their use with a general-purpose system software stack. Various works extend the SIMT model to support more generic code [22], [23] or more flexible execution [24], [25], [26]. However, they all target applications specifically written for GPUs, rather than general-purpose parallel applications.…”

Section: E Power and Energymentioning

confidence: 99%

Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP

Kalathingal

Collange

Swamy

et al. 2016

2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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Abstract-Threads of Single-Program Multiple-Data (SPMD) applications often execute the same instructions on different data. We propose the Dynamic Inter-Thread Vectorization Architecture (DITVA) to leverage this implicit data-level parallelism in SPMD applications by assembling dynamic vector instructions at runtime. DITVA extends an SIMD-enabled in-order SMT processor with an inter-thread vectorization execution mode. In this mode, multiple scalar threads running in lockstep share a single instruction stream and their respective instruction instances are aggregated into SIMD instructions. To balance thread-and data-level parallelism, threads are statically grouped into fixed-size independently scheduled warps. DITVA leverages existing SIMD units and maintains binary compatibility with existing CPU architectures.Our evaluation on the SPMD applications from the PARSEC and Rodinia OpenMP benchmarks shows that a 4-warp × 4-lane 4-issue DITVA architecture with a realistic bank-interleaved cache achieves 1.55× higher performance than a 4-thread 4-issue SMT architecture with AVX instructions while fetching and issuing 51% fewer instructions, achieving an overall 24% energy reduction.

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“…The main drawback of the context switch mechanism is that during the context save and restore, thread blocks do not progress, leading to a complete underutilization of the SM. This underutilization could be improved by using compiler-microarchitecture co-designed context minimization techniques, such as iGPU [22].…”

Section: Preemptive Kernel Executionmentioning

confidence: 99%

Enabling preemptive multiprogramming on GPUs

Tanasic

Gelado

Cabezas

et al. 2014

SIGARCH Comput. Archit. News

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GPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. However GPUs do not provide the support for resource sharing traditionally expected in these scenarios. Thus, such systems are unable to provide key multiprogrammed workload requirements, such as responsiveness, fairness or quality of service.In this paper, we propose a set of hardware extensions that allow GPUs to efficiently support multiprogrammed GPU workloads. We argue for preemptive multitasking and design two preemption mechanisms that can be used to implement GPU scheduling policies. We extend the architecture to allow concurrent execution of GPU kernels from different user processes and implement a scheduling policy that dynamically distributes the GPU cores among concurrently running kernels, according to their priorities. We extend the NVIDIA GK110 (Kepler) like GPU architecture with our proposals and evaluate them on a set of multiprogrammed workloads with up to eight concurrent processes. Our proposals improve execution time of high-priority processes by 15.6x, the average application turnaround time between 1.5x to 2x, and system fairness up to 3.4x.

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iGPU: Exception support and speculative execution on GPUs

Cited by 23 publications

References 35 publications

Static analysis and compiler design for idempotent processing

Static analysis and compiler design for idempotent processing

Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP

Enabling preemptive multiprogramming on GPUs

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