III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications

Tripathy, Manas Ranjan; Singh, Ashish Kumar; Baral, Kamalaksha; Singh, Prince Kumar

doi:10.1016/j.spmi.2020.106494

Cited by 43 publications

(12 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The impact of temperature variations on the IIP3 for DMSGO-TFET and DMSGO-SDP-TFET are illustrated in Figs. 10(a Table 3 Comparison of DC, analog/RF parameters with recent literature Parameters DMSGO-SDP-TFET Ref [33] Ref [34] Ref [35] Ref [23] Ref [36] I ON (A/µm) SDP-TFET is higher than DMSGO-TFET, this increase in the IIP3 parameter indicates improvement in the linearity performance of the device. Therefore, DMSGO-SDP-TFET shows better linearity compared to DMSGO-TFET.…”

Section: Temperature Sensitivity Analysis Of Linearity and Distortion...mentioning

confidence: 99%

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

2022

View full text Add to dashboard Cite

Temperature dependence performance variation is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, for the first time the impact of temperature variations ranging from 300K to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel-field-effect transistor (DMSGO-SDP-TFET) is investigated. In this regard, technology computer-aided design (TCAD) simulator is used to analyze DC, and analog/radio frequency performance parameters such as carrier concentration, energy band variation, band-to-band tunneling rate (BTBT), I DS − V GS characteristics, transconductance (g m ), cut off frequency (f T ), gain-bandwidth product (GBP), maximum oscillating frequency (f max ), transconductance frequency product (TFP), and transit time (τ ) considering the impact of temperature variations. Furthermore, linearity parameters such as third-order transconductance (g m3 ), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio frequency applications. Moreover, the performance of the proposed DMSGO-SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel-fieldeffect transistor (DMSGO-TFET). From the comparative analysis, in terms of % per kelvin, DMSGO-SDP-Dharmender (corresponding author)

show abstract

Section: Temperature Sensitivity Analysis Of Linearity and Distortion...mentioning

confidence: 99%

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

2022

View full text Add to dashboard Cite

show abstract

“…However, hetero TFETs has one major limitation which restricts its widespread applications and need rigorous research study to overcome it. Tripathy et al [ 15 ] discuss the key drawback of the heterojunction TFETs of high Ioff as compared to conventional silicon-based TFETs. Hence, apart from source material engineering, device structural engineering is implemented as alternate solution to enhance Ion and reduce Ioff of TFET device.…”

Section: Introductionmentioning

confidence: 99%

“…Hence, apart from source material engineering, device structural engineering is implemented as alternate solution to enhance Ion and reduce Ioff of TFET device. In this regard, different device architectures such as vertically grown TFET, L-shaped/U-shaped TFET, and source pocket engineered TFET have been explored and reported in literature [ 15 ]. The enclosed architecture as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Investigation of gate-engineered heterostructure tunnel field effect transistor as a label-free biosensor: a compact study

2023

View full text Add to dashboard Cite

In this article, the authors have articulated DC as well as transient response of a dielectric modulated gate-engineered heterostructure tunnel field effect transistor (GE-HTFET)-based biosensor for label-free detection. A low (direct) bandgap material, indium arsenide (InAs) has been selectively used in the source region to achieve improved band-to-band tunneling of carriers in the tunnel FET. The extended gate architecture is incorporated to stabilize the biomolecules in the nano-cavity aiding significant boost in ON current sensitivity. Using SILVACO ATLAS TCAD tool, the sensitivity of the biosensor is evaluated considering two important parameters possessed by bio-targets, i.e. dielectric constant ( k ) and charge density ( N ). A thorough analysis has been performed to show the impact of variation of dielectric constants and charge density of biomolecules over transfer characteristics of the device. ON current level (Ion) is eventually extracted which is considered here as the suitable sensing parameter of the device. Transient response to detect the settling time of Ion is also demonstrated here in presence of both positively and negatively charged bio-species with varying values of dielectric constant. Then ON current sensitivity is extracted accordingly for different locations of biomolecules within the nano-gap. Finally, an extensive comparative analysis of the present structure in terms of ON current sensitivity is shown to justify its sensing ability as compared to recently reported device structures.

show abstract

“…However, ambipolarity and lower ON-state current (I ON ) are two major limitations for TFETs [9]. To address these concerns, researchers proposed various device structures such as double-gate, dual material gate, workfunction engineering, material engineering, stacked gate oxide, pocket doping, electrically doped (ED), dielectric pocket, and gate over source overlap, and extended source TFET [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In addition to the above issues, the reliability issues that arise as a result of ITCs developed at the Si-SiO 2 interface due to variations in process, stress, radiation, and the effect of hot carriers are also major concerns [32][33][34][35][36][37][38].…”

Section: Introductionmentioning

confidence: 99%

Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

Dharmender

Nigam

Kumar

2022

Preprint

View full text Add to dashboard Cite

In this work, we have investigated the reliability of the extended source double gate tunnel field-effect transistor (ESDG-TFET) by considering the effect of the fixed donor (positive) and acceptor (negative) interface trap charges (ITCs) at the silicon-SiO2 interface and temperature variations ranging from 300K to 480K, on the DC, analog/radio frequency (RF), linearity and harmonic distortion performance parameters. A comparative analysis has been performed between conventional stack gate oxide double gate TFET (SGO-DG-TFET) and ESDG-TFET with similar dimensions. Different performance metrics such as transfer characteristics, parasitic capacitances, gain-bandwidth product (GBP), unity gain frequency (fT), transit time, transconductance frequency product (TFP), and linearity distortion performance parameters such as 2nd and 3rd order transconductance coefficients (gm2, gm3), 2nd and 3rd order voltage intercept points (VIP2, VIP3), 3rd order input intercept point, intermodulation distortion parameters (IIP3, IMD3), and 1dB compression point have been investigated. Moreover, 2nd and 3rd order harmonic distortions (HD2, HD3) and total harmonic distortion (THD) are investigated using technology computer-aided design (TCAD) simulations. The Tables 2, 3 and 4 show that in terms of percentage variation, ESDG-TFET exhibits less variation as compared to SGO-DG-TFET, which indicates that the ESDG-TFET is more immune to ITCs and temperature variations. Thus, ESDG-TFET can be used for low power switching and analog/RF and high temperature applications.

show abstract

III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications

Cited by 43 publications

References 22 publications

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

Investigation of gate-engineered heterostructure tunnel field effect transistor as a label-free biosensor: a compact study

Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

Contact Info

Product

Resources

About