ILP-based modulo scheduling for high-level synthesis

Abstract

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling.We propose Moovac 1 , a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-II solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution.We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger.Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation.Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of small-to medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate II. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final II.

Scaling Up Modulo Scheduling for High-Level Synthesis

“…Additionally to resources, other HLS metrics can be added in the ILP to improve or ensure hardware quality, as timing, chaining [8], and soft [9] constraints. Instead of separating the problem scheduling and allocation parts, [10] proposes to use the complete formulation, which always allows finding the optimal solution for a given II, if it exists. This formulation requires O(n 2 ) variables and constraints to ensure MRT validity, which arecalled overlap variables [11], where n is the loop size.…”

“…Formulation 1 presents a simplified version of the ILP formulation presented in [10], where the variables domain is described in Table II (replicated from [10]).…”

“…For each dependency on the data flow, a constraint is created (line 4), where b ij ≥ 0 is the loop-carried dependency distance (which is represented as a back-edge in the data-flow graph), and b ij = 0 for data dependencies (forward edges in the data flow). Note that [10] considers b ij ∈ {0, 1}, while this paper adopts the more general case where b ij ∈ Z + 0 , as proposed by [6].…”

“…Formulation 1: Simplified version of ILP formulation for modulo scheduling presented in [10] (1) minimize:…”

“…same MRT slot, the binary overlap variables ij (lines 5 to 7, and 11) and µ ij (lines 8 to 11) are defined for each pair of instructions I i and I j that share the same resource type k, making the number of overlap variables to grow quadratically with the loop size. Lines 4 and 15 capture the dependency and timing constraints used in [10]. Lines 13 and 14 provide the upper bounds for r i and m i , respectively.…”