IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Abstract

In-memory computing' is being widely explored as a novel computing paradigm to mitigate the well known memory bottleneck. This emerging paradigm aims at embedding some aspects of computations inside the memory array, thereby avoiding frequent and expensive movement of data between the compute unit and the storage memory. In-memory computing with respect to Silicon memories has been widely explored on various memory bit-cells. Embedding computation inside the 6 transistor (6T) SRAM array is of special interest since it is the most widely used on-chip memory. In this paper, we present a novel in-memory multiplication followed by accumulation operation capable of performing parallel dot products within 6T SRAM without any changes to the standard bitcell. We, further, study the effect of circuit non-idealities and process variations on the accuracy of the LeNet-5 and VGG neural network architectures against the MNIST and CIFAR-10 datasets, respectively. The proposed in-memory dot-product mechanism achieves 88.8% and 99% accuracy for the CIFAR-10 and MNIST, respectively. Compared to the standard von Neumann system, the proposed system is 6.24× better in energy consumption and 9.42× better in delay.

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

“…One of the main challenges faced during the realization of an IMC system is that the peripheral circuits, especially data converters that interface the crossbar array with the digital world, carry the largest energy overhead and could even dominate the associated latency and area footprint. In addition, voltage-based A/D converters (ADCs) are mostly used [31] that require a voltage to current conversion, usually employing a large capacitor for integration [23], [32]. This has thus far hampered the realization of large fully-parallel on-chip MVM operations at true O(1) complexity.…”

Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications

“…Assuming v t is a zero mean random variable with standard deviation σ Vt = Var(v t )) leads to (18) with σ Ij = Var(i j ).…”

“…Though CM uses both QS and QR compute models, the noise source from QR dominates. Specifically the noise due to current mismatch (18) dominates all other noise sources. In the presence of current mismatch noise, assuming the weight w j is positive, the discharge on the j-th BL in CM is given by:…”

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

“…Many approaches to Logic-In-Memory can be found in literature; however, two main approaches can be distinguished. The first one can be classified as Near-Memory Computing (NMC) [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], since the memory inner array is not modified and logic circuits are added at the periphery of this; the second one can be denoted as Logic-in-Memory (LiM) [19][20][21][22][23][24][25][26][27][28], since the memory cell is directly modified by adding logic circuits to it.…”

“…Many applications can benefit from the IMC approach, such as machine learning and deep learning algorithms [4,6,[8][9][10][11][12]14,15,19,[21][22][23][24], but also general purpose algorithms [2,5,7,13,[16][17][18]20,25,26]. For instance: in [19], a 6T SRAM cell is modified by adding two transistors and a capacitor to it, in order to perform analog computing on the whole memory, which allows to implement approximated arithmetic operations for machine learning algorithms; in [18], logic layers consisting of latches and LUTs are interleaved with memory ones in an SRAM array, in order to perform different kinds of logic operations directly inside the array; in [26], the pass transistors of the 6T SRAM cell are modified to perform logic operations directly in the cell, which allows the memory to function as an SRAM, a CAM (Content Addressable Memory) or a LiM architecture.…”