Image Hashing Based on SHA-3 Implemented on FPGA

Sideris, Argyrios; Sanida, Theodora; Tsiktsiris, Dimitris; Dasygenis, Minas

doi:10.1007/978-981-16-9952-8_44

Cited by 2 publications

(3 citation statements)

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“…21 Gaj K. et al (2010) [12] Virtex-6 282.7 1272 12.817 10.08 Jararweh Y. et al (2012) [11] Virtex- in the area. Finally, in the works [7,14,18] the researchers show a larger area and smaller frequency than we achieved with our architectures. In our architectures, the primary purpose was not to use an excessive growth of the cost of the area (Slices) so that the throughput (Gbps) and efficiency (Mbps/Slices) are not burdened.…”

Section: Discussionmentioning

confidence: 56%

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Acceleration of Image Processing with SHA-3 (Keccak) Algorithm using FPGA

Sideris¹,

Sanida²,

Tsiktsiris³

et al. 2022

J. Engg. Res. & Sci.

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In our digital world, the transmission of images between people has played an essential part in everyday communication. As a result, procedures to ensure the integrity and accuracy of the communicated data are required. Today, hashing is the most popular and secure way. This article focuses on the SHA-3 for hashing images dimensions 256 × 256 pixels with our custom implementations on the FPGA based on the Very High Speed Integrated Circuit Hardware Description Language (VHDL). We perform our experiments on the Intel Arria 10 GX FPGA and the Nios II processor. Also, our experiments with calculating metrics such as entropy, NPCR and UACI show that the SHA-3 is secure, reliable and has high application potential for hashing images. We propose designs to improve throughput, security, and efficiency criteria. We strengthened our design using the IP Block Floating Point Hardware 2 (FPH-2). Our experiments with the proposed implementation have shown increased throughput by 14.38% and efficiency by 13.95% of the SHA-3 algorithm. Finally, we compared our findings to other researchers' existing optimization methodologies, giving data that demonstrate our research's strengths.

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