We report a pixel-block scanning-image-segmentation very large scale integration (VLSI) architecture based on a region-growing approach. The input image is divided into pixel blocks in order to process parts of the image in parallel while the pixel status data of the complete image is stored in embedded memory banks. Using the two techniques of (i) limited scan to the boundary of each grown region and (ii) continued block-internal region growing, we have improved the overall segmentation speed and power consumption in comparison to a previous solution. We evaluated the segmentation performance by MATLAB simulation and with a complete application specific integrated circuit (ASIC) design in the case of a one-dimensional scan. Low power dissipation of 44.7 mW and a segmentation performance of 1,000 fps at 8.6 MHz could be achieved. For a two-dimensional scan the block shape and size can be chosen with increased flexibility, and can be optimized to fulfill many different segmentation-speed, power-consumption, and implementation-area requirements. In particular, the pixel-parallel segmentation-unit area can be drastically reduced to 1/10 by changing the pixel-block size from 80 Â 2 to 4 Â 4 pixels, which still enables real-time segmentation performance.