IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements

Kyo, Shorin; Koga, T.; Okazaki, Shinichiro

doi:10.1109/icip.2001.958109

Cited by 11 publications

(4 citation statements)

References 5 publications

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“…6 or a design of the single majority gate structure in Fig. 7 , according to equation (5). We can see that the size of a voter grows faster than the increase of the redundancy in an NIR circuit.…”

Section: N-tuple Interwoven Redundancy (Nir)mentioning

confidence: 98%

From massively parallel image processors to fault-tolerant nanocomputers

Han¹,

Jonker²

2004

Proceedings of the 17th International Conference on Pattern Recognition, 2004. ICPR 2004.

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Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regular structures and mainly local interconnections, SIMD or SIMD-like architectures have been proposed for a large-scale integration of recently developed quantum and nanoelectronic devices. In this paper, we present a fault-tolerant technique suitable for an implementation in nanoelectronics, the triplicated interwoven redundancy (TIR). The TIR is a general class of triple modular redundancy (TMR), but implemented with random interconnections. A prototype structure for an image processor is proposed for the implementation of the TIR technique and a simulation based reliability model is used to investigate its faulttolerance. The TIR is extended to higher orders, namely, the N-tuple interwoven redundancy (NIR), to achieve higher system reliabilities. It is shown that the reliability of a general TIR circuit is, in most cases, comparable with that of an equivalent TMR circuit, and that the design and implementation of restorative devices (voters) are important for the NIR (TIR) structure. Our study indicates that the NIR (TIR) is in particular suitable for an implementation by the manufacturing process of stochastically molecular assembly, and that it may be an effective faulttolerant technique for a massively parallel architecture based on molecular or nanoelectronic devices.

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Section: N-tuple Interwoven Redundancy (Nir)mentioning

confidence: 98%

From massively parallel image processors to fault-tolerant nanocomputers

Han¹,

Jonker²

2004

Proceedings of the 17th International Conference on Pattern Recognition, 2004. ICPR 2004.

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“…They show performance of up to 196.7 GMAs/Watt when fabricated in 65 nm technology. Other similar architectures, based on programmable cores with limited connectivity, were the IMAPCAR [129]/IMAP-CE CGRA [130] from NEC aimed towards image recognition in automobiles.…”

Section: Larger Cgrasmentioning

confidence: 99%

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

2020

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“…the PixelFusion graphics engine [31]). Especially promising are the prospects of SIMD arrays in systems-on-a-chip, particularly when based on SRAM cores [30], fused with CMOS sensor arrays [26], or implemented on platform FPGAs (see below). Other uses include network processors [11], signal and image processing [33], and bioinformatics [19].…”

Section: Introductionmentioning

confidence: 99%