Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC

Abstract

Due to the rise in the number of cores in modern multi-core architectures, 3D integration (i.e., vertical stacking of chips) of System-on-a-chip (SOC) promises better performance due to a drastic reduction in global interconnect lengths and die footprint compared to 2D counterparts. However, thermal issues are predominant in 3D-SOCs due to the vertical stacking nature of chips which multiplies the transistor power density by the number of dies within the stack. Also, the reduced lateral heat spreading with aggressive die thinning, degrades the on-chip thermal performances. In this paper, we investigate the thermal performance analysis of 3D-SOC and compare the results with the 2D-SOC designs for a MemPool multi-core SOC with shared L1 scratchpad memory (SPM). Simulation results reveal that the 3D-SOC using Memory on Logic configuration increases the on-chip maximum temperature by more than 20% compared to the baseline 2D-SOC and the logic die temperature is relatively higher (3.6%) than the memory die. We also explore the impact of architectural floor-planning effects and 3D functional partitioning on thermal performance of the MemPool instances in the 3D-SOC with memory capacity ranging from 1 MiB to 8 MiB and benchmarked the thermal performance with the 2D-SOC designs. We observe that the junction to ambient temperature (Tmax) increases by 44% and is predominant for the scratchpad memory (SPM) capacity of 8MiB. Further investigations on various 3D stacking configurations reveal there is an improvement in thermal performance for memory-on-logic (MOL) over logic-on-memory (LOM) for L1 SPM capacity of 1 MiB, 2 MiB and 4 MiB, and LOM over the MLL configuration for L1 SPM capacity of 8 MiB.

Research on the Mechanical Failure Risk Points of Ti/Cu/Ti/Au Metallization Layer

“…As chip integration continues to advance, the power density of microelectronic devices steadily increases, leading to a sharp rise in the internal temperature of the chips [1,2]. However, the traditional solder materials used in these devices exhibit insufficient thermal conductivity, preventing the chips from efficiently dissipating heat and resulting in potential thermal reliability issues.…”