Impact of ALD TiN Capping Layer on Interface Trap and Channel Hot Carrier Reliability of HKMG nMOSFETs

Yang, Hong; Luo, Wei; Zhou, Longda; Xu, Hao; Tang, Bo; Simoen, Eddy; Zhu, Huilong; Zhao, Chao; Wang, Wenwu; Ye, Tianchun

doi:10.1109/led.2018.2847906

Cited by 8 publications

(6 citation statements)

References 13 publications

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“…Furthermore, the film thickness is another important elementary to reliability issues. The atomic layer deposition Titanium Nitride (ALD TiN) layer plays a very important role in CMOS integration [ 296 , 297 , 298 , 299 ]. The devices with different thickness of ALD TiN show the similar electrical parameters, while the reliability issues of devices are obviously different.…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

“…The devices with different thickness of ALD TiN show the similar electrical parameters, while the reliability issues of devices are obviously different. Usually, the devices with thin ALD TiN layer show worse hot carrier injection (HCI) and better bias temperature instability (BTI) than that with thick ALD TiN due to the chlorine diffusion [ 10 , 296 ] and nitrogen diffusion [ 297 , 298 ], respectively. Therefore, it is key to restrain reliability degradation of advanced CMOS technology by controlling the process.…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Advanced Devices Reliablitymentioning

confidence: 99%

Section: Advanced Devices Reliablitymentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…The threshold voltage of the SiC Schottky barrier diode (SBD), which is connected in anti-parallel with the SiC MOSFET, is lower than that of the stray diode, and the measurement current ISD does not flow through the stray diode. Therefore, the voltage across the source (S)-drain (D) junction VSD across a stray diode generated by application of a negative gate voltage across the gate (G)-source (S) junction (VGS) is not applicable as a temperature-sensitive electrical parameter in this case [3]. Because of the presence of interface traps in the gate oxide layer of the SiC MOSFET, the threshold voltage and the other electrical parameters of the device tend to drift, which destroys both the repeatability of the temperature calibration curve and the accuracy of the junction temperature measurements.…”

Section: Introductionmentioning

confidence: 99%

Research on junction temperature of SiC MOSFET module

Ding

Guo

et al. 2023

Second International Conference on Advanced Manufacturing Technology and Manufacturing Systems (ICAMTMS 2023)

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Silicon carbide (SiC)-based wide-bandgap semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) generate large amounts of heat because of their small size and increasingly high power density. The junction temperature is the most important index for evaluation of the reliability of these devices. This article proposes a method to study the changes in the forward voltage across the drain (D)-source (S) junction (VDS) under various test conditions from the perspectives of temperature sensitivity, stability, repeatability, and anti-interference properties, with the aim of determining suitable temperature test conditions for SiC MOSFET chips to achieve precise device temperature measurements. The accuracy of the proposed measurement method is verified via comparison with an infrared thermal imaging method and an electrical method. The results obtained show that the error in the SiC MOSFET junction temperature (Tj) measurements when compared with the infrared method and the electrical method is around 1%.

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“…TiN in the stack with HfO 2 has a EWF range between 4.4 and 4.9 eV, depending on processing technique used and the metal layer thickness [34,35] and meets the requirement for pMOS. TiN is a widely used material in conventional IC process, so induces no contamination risk.…”

mentioning

confidence: 95%

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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Impact of ALD TiN Capping Layer on Interface Trap and Channel Hot Carrier Reliability of HKMG nMOSFETs

Cited by 8 publications

References 13 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Research on junction temperature of SiC MOSFET module

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

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