Impact of CD and overlay errors on double-patterning processes

Abstract

Double patterning (DP) is today the main solution to extend immersion lithography to the 32 nm node and beyond. Pitch splitting process with hardmask transfer and spacer process have been developed at CEA-LETI-Minatec. This paper focuses on experimental data using dry ArF lithography with a k 1 factor of 0.20 ; the relative impact of each DP step on overlay and CD uniformity budgets is analyzed. In addition, topography issues related to the presence of the patterned hard mask layer during the second imaging step is also investigated. Tool-to-itself overlay, image placement on the reticle and wafer deformation induced by this DP process are evaluated experimentally and resulting errors on CD budget have been determined. CD uniformity error model developed by Nikon describing the relationship between CD and overlay in different DP processes is validated experimentally.

Integration of dry etching steps for double patterning and spacer patterning processes

“…In the optimized case, the average CD after ETCH1 is only decreased by 3nm during ETCH2, which is consistent with the cross-section SEM pictures presented above (Fig. 6) Concerning the CD uniformity across the wafer, the etching steps do not induce additional non uniformity during the DP line sequence [4]. …”

“…The intra-field CD uniformity is around 2.6nm at litho1 and 3.3nm at litho2 , thus well below ITRS requirements. PW reduction and CDU increase at litho2 are due to topography effects as discussed in another paper, where more details about litho performances are given [4]. The final CD target of 45nm is achieved thanks to a resist trimming step included in the etching sequence.…”

Chemically amplified phenolic fullerene electron beam resist

“…As a control, Rohm and Haas SAL601, a highdurability novolac-based conventional resist, was etched as well. For SF 6 selectivity in contrast to the control, which was removed at a rate of 1.24 nm s À1 with 2.77 : 1 selectivity. The increase in selectivity between the two gas mixtures is caused by the higher silicon etch rate of the SF 6 /CHF 3 gas mix.…”

“…The gas mixture used was either SF 6 /CHF 3 or SF 6 / C 4 F 8 . The process conditions were 15 sccm SF 6 Aerwards the residual resist was stripped with oxygen plasma and the height of the silicon features measured again. The etch rate of the resist material was then calculated from these measurements.…”

“…The International Technology Roadmap for Semiconductors (ITRS) 3 has specied 20 nm DRAM half-pitch (hp) and 14 nm Flash halfpitch as target resist requirements for 2016. Whilst it has been possible to extend current 193 nm photolithography far beyond expectation, to allow sub-30 nm patterning, 4,5 this has been at the cost of greatly increased complexity of the patterning or post-exposure processing, 6 which dramatically impacts yield and cost. Electron-beam lithography (EBL), traditionally considered to be high-resolution but slow, has primarily found application in the semiconductor industry for the fabrication of reticles.…”