Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Ito, Y.; Fukushima, T.; Kino, Hisashi; Lee, Kangwook; Tanaka, Tetsu; Koyanagi, Mitsumasa

doi:10.1109/jmems.2015.2480787

Cited by 11 publications

(6 citation statements)

References 38 publications

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“…A few studies analysed the influence of the component feeding offset on the success of capillary self-alignment. 26,53,72,120 Sariola et al experimentally investigated the alignment yield upon varying translational biases of sub-millimeter square components. 60 The main result was that the yield dropped much faster with normal bias than with lateral bias, because lateral bias only shears the meniscus, while normal bias can result in either bulging of the liquid from the sides or necking of the meniscus (Fig.…”

Section: Component Feedingmentioning

confidence: 99%

Surface tension-driven self-alignment

et al. 2017

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Surface tension-driven self-alignment is a passive and highly-accurate positioning mechanism that can significantly simplify and enhance the construction of advanced microsystems. After years of research, demonstrations and developments, the surface engineering and manufacturing technology enabling capillary self-alignment has achieved a degree of maturity conducive to a successful transfer to industrial practice. In view of this transition, a broad and accessible review of the physics, material science and applications of capillary self-alignment is presented. Statics and dynamics of the self-aligning action of deformed liquid bridges are explained through simple models and experiments, and all fundamental aspects of surface patterning and conditioning, of choice, deposition and confinement of liquids, and of component feeding and interconnection to substrates are illustrated through relevant applications in micro- and nanotechnology. A final outline addresses remaining challenges and additional extensions envisioned to further spread the use and fully exploit the potential of the technique.

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Section: Component Feedingmentioning

confidence: 99%

Surface tension-driven self-alignment

et al. 2017

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“…On the way to final positioning in self-assembly processes, the chips are often fixed due to the chip own weight against restoring forces driven by water surface tension and/or friction force from host wafers (hydrophobic surfaces) due to the chip tilt. The big statistics is also mainly attributed to the manual chip handling (not well controlled chip pre-positioning), giving large initial offsets in x / y / z /θ directions in addition to chip tilt prior to chip landing onto the top of the water droplets immediately after chip release [ 40 , 41 , 42 , 43 ]. We can further increase the alignment accuracies and reduce the variation by chip thickness reduction down to 100 μm or below, by the use of automatic/robotic chip handling systems, and by optimization of lithographic conditions using steppers to define the vernier positions toward outer sizes of the corresponding hydrophilic assembly areas.…”

Section: Resultsmentioning

confidence: 99%

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

et al. 2016

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Plasma- and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

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“…Chips fabricated by plasma dicing before grinding technique have high-precision chip size accuracy ±1 m, and thereby, high alignment accuracies of approximately 0.4 m have been obtained (16). Standard saw dicing can provide high chip size accuracies ±1-2 m, which have high potential to achieve submicron alignment accuracies (32).…”

Section: Capillary Self-assemblymentioning

confidence: 99%

“…However, chip-towafer 3D integration potentially has a trade-off between assembly throughput and alignment accuracies in the conventional robotic pick-and-place techniques. In order to address the problems, we have proposed and developed multichip-to-wafer 3D integration using liquid surface tension (1)- (32). From the technical point of view of chipto-wafer bonding, we talk about the basic concept and previous studies of the selfassembly based 3D integration.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

Fukushima¹,

Lee²,

Tanaka³

et al. 2016

ECS Trans.

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We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid in this decade. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configuration are introduced for fine-pitch interconnect formation. In addition, “non-transfer stacking”, in other word, flip-chip self-assembly and “transfer stacking” called reconfigure-wafer-to-wafer using SAE carrier are explained.

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Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration

Cited by 11 publications

References 38 publications

Surface tension-driven self-alignment

Surface tension-driven self-alignment

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

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