Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array

Kempf, Thibault; Mantelli, M.; Maugain, F.; Régnier, A.; Portal, Jean‐Michel; Masson, Pascal Le; Moragues, Jean-Michel; Hesse, Marjorie; Marca, V. Della; Julien, Franck; Niel, S.

doi:10.1109/iirw.2017.8361234

Cited by 1 publication

(1 citation statement)

References 14 publications

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“…Our test chip, described in Fig. 2(a) [17], is a MCU embedding a memory cut of our Flash technology. The array is based on a butterfly architecture, i.e.…”

Section: B Test Chip Descriptionmentioning

confidence: 99%

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

Kempf¹,

Marca²,

Baron³

et al. 2018

2018 IEEE International Reliability Physics Symposium (IRPS)

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The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs testchips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is based first on analog bitmap acquisition on 512kB testchip, followed by correction of spatial variabilities like peripheral circuit influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally such an analysis tool enhances the advantageous properties of test chip, its large memory cell statistics and its product-like organization, to give more reliable data and yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level. I. Criteria Test structure Single device Test chip Statistics availability Low bits density High bits density Cell envirronement Limited Product like Memory defectivity Memory only Peripheral effect, memory array organization/ intersite variation Test time Low Need burn-in, or early failure binning (EWS) Test flexibility High. Limited by its embedded test modes (BIST, reliability test, DMA…) and register values.

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“…Our test chip, described in Fig. 2(a) [17], is a MCU embedding a memory cut of our Flash technology. The array is based on a butterfly architecture, i.e.…”

Section: B Test Chip Descriptionmentioning

confidence: 99%