Impact of deep and tail trap states on the electrical performance of double-gate ZnO thin film transistors

Abstract

Traps in the ZnO TFTs affect the electrical characteristics of the device. Traps originate primarily due to the disordered nature of the deposited semiconductor channel or present at the ZnO and gate-dielectric interface. This work studies the effect of traps in double-gate ZnO TFT using TCAD. The grain boundary (GB) and interface traps are assumed to be localized at the ZnO/SiO2 interface and are defined within the energy bandgap of ZnO using a double exponential function. The nature of traps is assumed to be acceptor-type. The concentration of tail states is assumed to be 103 times more than the deep state, while the characteristic temperature of deep state traps is assumed to be higher than the tail states. In common mode operation (both top and bottom gates are shorted), the tail states dominated the device characteristic compared to the deep state. While in independent mode (both gates are biased independently), the deep state traps affect the device characteristics more than the tail states.