Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Abstract

This article presents the reliability analysis of a High-k stacked Dual Gate Junction-less MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and RF stability performance metrics. Furthermore, the dc and analog figure of merits in the presence polarized interface trap charge densities has been analyzed at subambient temperatures. The steep ON-OFF switching and the sub-threshold slope profile shows heavy reliance on temperature variations and confirm that the transistor electrostatics improve at lower temperatures. The study reveals the compatibility of the device to perform at cryogenic temperatures and can be integrated with CMOS technology for quantum computations.

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

“…Since the gate electrodes on numerous sides of JLFETs with multiple gate topologies may quickly drain the whole silicon film, volume depletion is a simple process to do [ 7 ]. By reducing the SCEs, the DG-JLFET with hafnium oxide (HfO 2 ) demonstrates outstanding accomplishment [ 14 , 15 ]. The JLDG-MOSFET with high-k dielectric shows better I ON \I OFF , threshold voltage, and lowers the subthreshold swing compared to the conventional DG MOSFET [ 16 ].…”