Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories

Marca, V. Della; Postel-Pellerin, J.; Just, G.; Canet, P.; Ogier, Jean-Luc

doi:10.1016/j.microrel.2014.07.063

Cited by 13 publications

(17 citation statements)

References 9 publications

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“…An Agilent 16440A selector switches between the SMU and SPGU during the endurance test. The additional WGFMU in the setup, connected via RSU (Remote-Sense and Switch Unit) enables the definition of arbitrary waveforms and the dynamic measurement of the drain current, which can be useful when evaluating the consumption of the programming operation during the endurance test [14], [15].…”

Section: Methodsmentioning

confidence: 99%

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Enhancement of flash memory endurance using short pulsed program/erase signals

Chiquet¹,

Postel-Pellerin²,

Tuninetti³

et al. 2016

ACTA IMEKO

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The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent under polarization by the MOS-based devices. After a brief presentation of the functioning of the Flash memory transistors tested in this work, the experimental setup used to replace standard electric signals with short pulses will be described. Electrical results showing the benefits of programming and erasing non-volatile memories with short pulses will then be presented.

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Section: Methodsmentioning

confidence: 99%

“…Energy consumption of non-volatile memory devices has been of recent interest as experimental possibilities offered with the coming of new parameter analyzers in recent years [14], [15]. It can be defined according to the following equation 4:…”

Section: Measurement Of Device Consumptionmentioning

confidence: 99%

Enhancement of flash memory endurance using short pulsed program/erase signals

Chiquet¹,

Postel-Pellerin²,

Tuninetti³

et al. 2016

ACTA IMEKO

View full text Add to dashboard Cite

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“…From this perpendicular design between the bottom gate line and word line, it is possible to program the selected cell only and inhibit programming of unselected cells, as described in the following paragraph. For programming, the FN tunneling mechanism is used instead of the hot-carrier injection (HCI) mechanism, which has been widely adopted for the conventional programming method in the NOR flash array [48][49][50]. This is because the conventional HCI programming consumes significant power due to a significant drain current during programming [48].…”

Section: Demonstration Of Nor Flash Array With the Proposed Memory Dementioning

confidence: 99%

“…For programming, the FN tunneling mechanism is used instead of the hot-carrier injection (HCI) mechanism, which has been widely adopted for the conventional programming method in the NOR flash array [48][49][50]. This is because the conventional HCI programming consumes significant power due to a significant drain current during programming [48]. On the other hand, FN programming can lower power consumption [37] due to its lower gate current compared to the higher drain current during HCI programming [48].…”

Section: Demonstration Of Nor Flash Array With the Proposed Memory Dementioning

confidence: 99%

“…This is because the conventional HCI programming consumes significant power due to a significant drain current during programming [48]. On the other hand, FN programming can lower power consumption [37] due to its lower gate current compared to the higher drain current during HCI programming [48]. Therefore, FN tunneling is adopted for programming with low power consumption.…”

Section: Demonstration Of Nor Flash Array With the Proposed Memory Dementioning

confidence: 99%

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Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Song

Park

2021

Micromachines

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For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

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Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories

Cited by 13 publications

References 9 publications

Enhancement of flash memory endurance using short pulsed program/erase signals

Enhancement of flash memory endurance using short pulsed program/erase signals

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Review of Semiconductor Flash Memory Devices for Material and Process Issues

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