Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Abstract

For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension based on device level parameters drift is difficult to handle, an accurate BD model is thus mandatory for predictive simulations at circuit level. Two dedicated test structures have been designed to track BD events impact on logic gates. Different AC-DC conditions are examined to be closer to operating conditions of digital circuits. Then a compact model for BD in logic gates is proposed: according to device level measurements, different severities of the BD event impact can be selected. Next Monte Carlo simulations are performed and enable to discuss the real impact of BD on logic gates in comparison with the measurements. In this way the measurements at device and circuit levels can be linked and the most likely post-BD device characteristics are highlighted. Therefore, the real impact of hard BD can be mitigated.

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

“…Figure 7 illustrates the breakdown probability with operation time duration of MTJ and nNOS/pMOS transistors. The curves of FD-SOI transistors show agreement with the experimental data in [47]. The stress voltage applied on MTJ oxide barrier is around 400 mV, whereas CMOS transistor is biased with 1 V gate voltage.…”

“…The reliability of hybrid CMOS/magnetic integration is a major concern for circuit designers in the near future [43][44][45][46][47][48][49]. The integration of unreliable, deep-scaled nanometer CMOS and MTJ processes pose tremendous challenges from the device level up to system level.…”

“…With the continuous scaling of CMOS technology nodes, MRAM with design-for-reliability is required due to the impacts of parametric process variations, aging mechanisms and transient faults [35,36,[45][46][47][48]. In this section, the process variation, thermal variation and breakdown are reviewed for reliable MRAM design.…”

“…The MTJ oxide barrier thickness is lower than FD-SOI CMOS oxide, which is around 1 nm [46]. The probability of breakdown occurrence in CMOS devices follows the Weibull distribution [47]. Figure 7 illustrates the breakdown probability with operation time duration of MTJ and nNOS/pMOS transistors.…”

CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range

“…We study in this section Wearout mechanisms under HCD and BTI as a rule of thumb for a front-end analysis of digital application. Timedependent dielectric breakdown (TDDB) can also be a limiting reliability criterion in CMOS technology using high-voltage (thick gate-oxide) to low-voltage (thin EOT) logic blocks [18] . However, recent works have shown that the VDD reduction and frequency increase up to 1 GHz induce a clear improvement in AC-TDDB [19] , leading to a smaller failure rate at low voltage and high frequency.…”