Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device

Abstract

In this paper, we investigate the impact of process parameter like halo structure on threshold voltage (V TH ) and leakage current (I Leak ) in 45nm NMOS device. The settings of process parameters were determined by using Taguchi experimental design method. Besides halo implant, the other process parameters which used were Source/Drain (S/D) implant and oxide growth temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to threshold voltage and leakage current are oxide growth temperature (71%) and S/D implant dose (47%) respectively. Whereas the second ranking factor affecting V TH and I Leak are halo implant tilt (15%) and halo implant dose (35%) respectively. As conclusions, S/D implant dose and oxide growth temperature have the strongest effect on the response characteristics. The results show that the V TH for NMOS device equal to 0.150V at tox= 1.1nm. The results show that I Leak after optimizations approaches is 51.8µA/µm.

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

“…In our work, we have increased the gate oxide thickness by 2 Å (from 26 Å to 28 Å) to optimize the leakage property of the device performance. Meanwhile, the doping concentration during the well definition step is also lowered by 0.1×10 13 cm -3 accordingly, in order to adjust the Vth value of the engineered UHVT device to the same level of the standard HVT device for a comparable device performance [15][16][17][18] .…”