Impact of high k spacer on RF stability performance of double gate junctionless transistor

Abstract

In this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut-off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability. KEYWORDS double gate junctionless transistor (DGJLT), high k spacer, MAG, MSG, RF stability, unity gain cutoff frequency 1 | INTRODUCTIONAccording to the International Technology Roadmap for Semiconductors, alternative metal-oxide-semiconductor field-effect transistor (MOSFET) structures serve the need for devices beyond 16 nm. 1 One of the promising devices which can substitute the conventional MOSFET is junctionless transistor (JLT). 2 Junctionless transistor does not have PN junctions because source, channel, and drain are of same doping, which overcomes the problems associated with doping profile of MOSFETs. It also offers many advantages over conventional bulk MOSFETs such as better scalability, reduced short channel effects, simple fabrication process flow, and low thermal budgets after gate formation. [3][4][5] The JLT has received attention for analog/radio frequency (RF) applications due to its improved intrinsic gain and maximum oscillation frequency ( f max ). 6 Many works were carried on JLTs about enhancing the electrostatic integrity using a high k spacer, drain/source extension, and gate work function on analog and RF applications. 7-12 Impact of process parameter variation on the analog and RF performance of the multigate is studied. 13 The RF model was developed to extract the parameters like cut-off frequency ( f T ), input capacitance, and distribute channel resistance of junctionless silicon nanowire MOSFET. 14 The quantum mechanical model of gate all around nanowire MOSFET is developed to examine the effect of high k gate dielectric on the electrostatics and device performance. 15 The reliability issues of graded channel junctionless multigate transistor in analog performance are investigated. 16 From the literature review, we found that many studies were carried on analog and RF performance of JLTs. However, RF stability study on JLTs is not reported, which is an important figure of merit for the design of RF amplifiers or

Study of enhanced DC and analog/radio frequency performance of a vertical super‐thin body FET by high‐k gate dielectrics

“…Finally, to evaluate the significance of a VSTB FET, it is necessary to compare its performance to that of other non‐classical devices. In this regard, the overall performance estimated in this work is compared with the reported results of few published articles in Table 3 17,18,48–56 . It is noticed that a VSTB FET yields a comparable performance as any other modern device; however, the structural complexity is minimal in the case of this new structure.…”

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

“…As a result, the material with higher‐ k causes to have better results in I ON and I OFF current. [ 27,28 ] Table 3 demonstrates the efficacy of several spacer oxides on the effectiveness of the EPL‐JLT device at WF = 5 eV. The EPL‐JLT obtains the largest V TH with HfO 2 spacer and the smallest belongs to air spacer.…”

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

“…Many researchers are working on the analytical modeling, simulation and fabrication of such technologybased devices. Different studies have been carried out in the literature to obtain better results by applying various ideas on the device structures such as high K dielectric materials [20][21][22], different semiconductor materials [23][24][25][26], high K spacers [27][28][29], mobility enhancement using strain technology [30][31][32][33]. Moreover, multi-gate junctionless transistors to improve gate control have also been studied [12,27,[34][35][36][37][38][39][40][41].…”