Impact of Iterative Deuterium Annealing in Long-Channel MOSFET Performance

Abstract

In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative impact of HPD for the better fabrication of semiconductor devices. Long-channel gate-enclosed FETs are fabricated as a test vehicle. After each cycle of the annealing, device parameters are extracted and compared depending on the number of the HPD. Based on the results, an HPD condition that maximizes on-state current (ION) but minimizes off-state current (IOFF) can be provided.

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

“…The gate field effect controls the conduction of current in a very thin, highly doped semiconductor layer. Because junctionless transistors don't have source and drain junctions, they don't need to build ultra-steep junctions 7 or do a lot of thermal annealing 8 for S/D dopant activation is a significant advantage. Also, the fabrication process is easier because there are no lateral diffused drains, 9 pocket implantations, 10 or shallow junctions anymore.…”