Impact of level 2 cache and memory subsystem on the scalability of clusters of small-scale SMP servers

Bus) Cache size MemoryHigh-perfbrmance computing has increasingly adopted the use of clustered Intel architecture-based servers. This increase in udopfion has been largely fueled by n number gf technological enhancements in the Intel architeciure-based servers, primarily due to substantial improvement in the Intel processor and m m o y technology over the past few years. MHz L2: 512 L2: I MB L2: 256 MB KB L3: 6 MB L3: 1 ME 4 x l G B 2 x 2 C B 4 x IGB MHz MHz 266MHz DDR-266 DDR2-400 DDR---This paper compares the performance characteristics of three Dell PawerEdge (PE) servers that are based on three different Intel processor technologies. They are the PEI 750 which is on IA-32 based Xeon system. PE1850 which uses the new 90nm technology Xeon processor at faster,Ji.eguencies and the PE3250 which is an lianium2 based system. Memory 4.2 GB/s 6.4 GBis BLAST (Basic Local Alignment Search Tooo~), a high peyformance compu/ing application used in the field of biological research. i s used as the workloadfor h i s study. The aim is 10 urtdersfund the performance impact of the d@ierent /eotures associated with each processor/plaflorm technology when running the BLAST workload 6.4 GWs

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Impact of level 2 cache and memory subsystem on the scalability of clusters of small-scale SMP servers

Cited by 2 publications

References 6 publications

Performance impact of process mapping on small-scale SMP clusters -a case study using high performance linpack

Performance impact of process mapping on small-scale SMP clusters -a case study using high performance linpack

Evaluating performance of BLAST on intel xeon and itanium2 processors

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