Impact of low K dielectrics on microelectronics reliability

Scansen, D.; Haythornthwaite, R.F.; Brown, S. L.

doi:10.1109/ccece.2005.1557029

Cited by 6 publications

(3 citation statements)

References 1 publication

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“…Corrosion of metals can also occur after moisture enters through the defective insulation. SEM cross sections will be used to exemplify real problems that have been observed during structural and failure analyses performed on production devices [20].…”

Section: Impact Of Low K Dielectrics On Microelectronics Reliabilitymentioning

confidence: 99%

Corrosion problems in electronic systems

Sivakumar¹,

Rajendran²,

Jancyrani³

et al. 2019

Zaštita materijala

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Microelectronics and, chiefly, silicon integrated circuit microelectronics, has created astonishing capabilities over the last 40 years. Speedy advancement in CMOS transistor equipment leading to the gigahertz speeds common today has necessitated chief changes in semiconductor manufacturing technology and the expansion of high frequency compatible packaging. The progress of an optimized formulation for electroless nickel (EN) plating with a long life span to make a deposit with good corrosion resistance (CR). The electroless deposition of NiP alloys is widely used in diverse fields such as aerospace, automation, electronics, nuclear, oil and gas production, and valve industries. Lead frame is the primary package metallurgical bond pad interface in microelectronic devices which provides external interconnection. The most predominant lead frame material is copper with tin plating. Over the years, galvanic corrosion and copper oxidation are two major reliability concerns for any microelectronics packages with copper lead frame, when operating under high humidity environment.

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Section: Impact Of Low K Dielectrics On Microelectronics Reliabilitymentioning

confidence: 99%

Corrosion problems in electronic systems

Sivakumar¹,

Rajendran²,

Jancyrani³

et al. 2019

Zaštita materijala

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“…On the other hand, with the critical dimension reduction, stresses induced by both front-end of line (FEOL) and back-end processes like wire bonding tend to increase [3,4]. Delamination failure modes are now commonly observed and mechanical integrity of IC has became a key integration issue [5]. Modeling is one of the major tools used to understand and reduce mechanical related defects.…”

Section: Introductionmentioning

confidence: 99%

3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments

Fiori

Beng²,

Downey³

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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Amongst solutions to connect the die to the package, thermosonic wire bonding process remains widely used. However, the introduction of low-k dielectric materials, and the feature size decrease of IC chips to follow Moore's law, pose great integration challenge.This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in the copper/low-k stack are evaluated. The modeling strategy also includes an in-house developed energy based analysis.For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, several bond pad architectures have been implemented and wire bonded on a test vehicle. It was found a significant effect of the copper/low-k design on peeling failure rates, in particular with severe bonding conditions. In this paper, typical modeling results are presented. Contrary to stress based one, the energy based analysis shows a better ability to forecast the observed failed interface. From simulation results obtained, it is confirmed that the bonding process plays major role in the peeling failure, despite the fact that most of them are observed during the wire pull test. Failure mechanisms are also proposed. Then, the implemented pad structures are evaluated and analyzed. Both general trends and architecture ranking are provided. Simulations are then faced to experimental results and a full agreement is found. The complementary nature of the energy based failure criteria is again highlighted through a clearer discrimination of the tested structures.Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.

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“…There are many parameters for consideration, among which the compatibility with the processing steps is that has to be investigated before device applications are implemented. Mechanical reliability or strength is another important requirement because if the low k dielectric materials cannot withstand stresses subjected to during processing, then the structural integrity of the entire interconnect can be compromised [39][40][41][42][43][44][45].…”

Section: Requirements For Low-k Dielectric Materialsmentioning

confidence: 99%

Application of carbon nanotubes (CNTS) in copper/low k interconnects design

Loo¹

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The author would like to express his gratitude to his supervisor Asst Prof Sridhar Idapalapati from School of Mechanical and Aerospace Engineering (MAE), NTU, for his comments and suggestions for improvements. In addition, he would also like to thank Asst Prof Lance Li, Asst Prof Zhou Jijie and Assoc Prof Subodh from School of Materials Science and Engineering (MSE) for their suggestions, advice and helpful discussions regarding the applications of Carbon nanotubes (CNTs). He would also like to thank Dr Valery Nosik and Dr Wang Shanzhong, Charles from ST Nanotube Centre for their help in carbon nanotube growth and supervision on the industrial relevance of the project. He also would like to thank Dr Tee Tong Yan and Dr Zhang Xueren for their advice in package development. Last but not least, the author is grateful to all who have rendered their aid to him in one way or another and is truly appreciative of them all.

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Impact of low K dielectrics on microelectronics reliability

Cited by 6 publications

References 1 publication

Corrosion problems in electronic systems

Corrosion problems in electronic systems

3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments

Application of carbon nanotubes (CNTS) in copper/low k interconnects design

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