Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of &amp;#x226A;100&amp;#x226B; or &amp;#x226A;110&amp;#x226B; oriented FDSOI cMOSFETs for the 32nm Node

Andrieu, F.; Faynot, O.; Rochette, F.; Barbé, J. C.; Buj, C.; Bogumilowicz, Y.; Allain, F.; Delaye, V.; Lafond, D.; Aussenac, F.; Eymery, J.; Akatsu, T.; Maury, P.; Brévard, L.; Tosti, L.; Dansas, H.; Rouchouze, Eric; Hartmann, Jean‐Michel; Vandroux, L.; Cassé, M.; Bœuf, F.; Fenouillet-Béranger, C.; Brunier, F.; Cayrefourcq, I.; Mazuré, C.; Gbibaudo, G.; Deleonibus, S.

doi:10.1109/vlsit.2007.4339723

Cited by 24 publications

(15 citation statements)

References 3 publications

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“…This effect can be seen in FDSOI films [29,32] where the biaxial and uniaxial strain are additive effects. This balances the loss of strain that could be induced by the source and drain and process steps to impl- ant contacts.…”

Section: Boosting the Performances Of Complementary Mosfets By Strainmentioning

confidence: 92%

“…For sub-100-nm range channel lengths and widths, the strain induced by the nearby thin films affects the device characteristics [31]. The loss of global strain observed in short channels is recovered by the lateral strain induced on the narrow active areas (Figure 8(a)) [29,[31][32][33].…”

Section: Boosting the Performances Of Complementary Mosfets By Strainmentioning

confidence: 99%

“…(Inset) Approximation of the used piezo-electric model[31]. Short and narrow n-channel electron mobility vs.inversion charge along orientations, (b) 110 and (c) 100[32,33].…”

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confidence: 99%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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Section: Boosting the Performances Of Complementary Mosfets By Strainmentioning

confidence: 92%

Section: Boosting the Performances Of Complementary Mosfets By Strainmentioning

confidence: 99%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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“…In this context, Silicon-On-Insulator (SOI) technology is increasingly used to process high performance and low power circuits. The planar SOI technology is an excellent candidate to reach specifications for future technologies [1] but their performances could be improved with innovative technological options such as: a front gate stack including a high permittivity (high-k) dielectric and a metal gate, or increased carrier mobilities due to mechanical stress induced in the active silicon area [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Investigations of the ionizing radiation induced effects in ultra-thin strained-silicon layers on insulator using confocal microscopy measurements

Gaillardin

Girard

Ouerdane

et al. 2011

Journal of Non-Crystalline Solids

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“…Strained SiliconOn-Insulator (sSOI) lines are considered due to their strong interest for enhancing the carrier mobility in metal oxide semiconductors field-effect-transistors (MOSFET) devices [17,18].…”

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confidence: 99%

Time-Dependent Relaxation of Strained Silicon-on-Insulator Lines Using a Partially Coherent X-Ray Nanobeam

et al. 2013

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We report on the quantitative determination of the strain map in a strained Silicon-On-Insulator (sSOI) line with a 200 × 70 nm 2 cross-section. In order to study a single line as a function of time, we used an X-ray nanobeam with relaxed coherence properties as a compromise between beam size, coherence and intensity. We demonstrate how it is possible to reconstruct the line deformation at the nanoscale, and follow its evolution as the line relaxes under the influence of the X-ray nanobeam.PACS numbers: 41.50.+h, 68.60.Bs New applications in optoelectronic and electronic semiconductor devices have been achieved by a careful control of strain at the nanoscale level. Several physical properties such as charge carrier mobility in transistors and emission wavelength in quantum dots or well heterostructure have been advantageously improved by applying strain fields adapted to the materials band structure, orientation and doping features [1][2][3][4].The measurement of these strain fields has required the development of dedicated techniques with adapted spatial and strain resolution. Electronic imaging techniques have seen tremendous developments and outstanding achievements [5], but are always limited by the preparation of thin foil that can considerably relieve internal stress in nanostructures. Very recently, X-ray diffraction has taken profit of the highly brilliant and coherent radiation provided by synchrotron sources [6]. Moreover, the optimization of dedicated focusing optics (compound refractive lenses [7], Fresnel Zone Plate (FZP) [8,9], Kirkpatrick-Baez mirrors [10,11]) has allowed the use of nanobeams, increasing the spatial resolution of diffraction measurements. This also allowed the use of coherent X-ray diffraction imaging (CXDI) for structure (shape, size) and strain determination of single nano-objects [12][13][14][15][16].In this letter, we illustrate how the strain of a single strained silicon nanostructure changes during irradiation with x-rays, as a function of measurement time using a partially coherent X-ray nanobeam. Strained SiliconOn-Insulator (sSOI) lines are considered due to their strong interest for enhancing the carrier mobility in metal oxide semiconductors field-effect-transistors (MOSFET) devices [17,18].Silicon lines were etched from a (001) oriented sSOI substrate made by a wafer bonding technique from the Si deposition on a SiGe virtual substrate imposing a biaxial strain, as described in [19]. Lines in tensile strain ( yy = +0.78%) are oriented along the [110] direction which corresponds to the usual direction of n-MOSFET channels for which electron transport is improved. The strain relaxes elastically along [110], i.e. perpendicularly to the lines [18]. An in-plane misorientation of about 1 o is used between the strained Si lines and the Si substrate in order to separate the line and substrate Bragg peaks. The sSOI lines have a width W=225 nm and a height H=70 nm (Fig. 1) and lie on a 145 nm SiO 2 layer. The distance d between two adjacent lines is about 775 nm. Grazing-incid...

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Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of ≪100≫ or ≪110≫ oriented FDSOI cMOSFETs for the 32nm Node

Cited by 24 publications

References 3 publications

Ultra-thin films and multigate devices architectures for future CMOS scaling

Ultra-thin films and multigate devices architectures for future CMOS scaling

Investigations of the ionizing radiation induced effects in ultra-thin strained-silicon layers on insulator using confocal microscopy measurements

Time-Dependent Relaxation of Strained Silicon-on-Insulator Lines Using a Partially Coherent X-Ray Nanobeam

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