Impact of NBTI and HCI on PMOSFET threshold voltage drift

Chaparala, P.; Brisbin, D.

doi:10.1016/j.microrel.2004.03.016

Cited by 19 publications

(7 citation statements)

References 10 publications

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“…Furthermore, the measurement data are compared to a simulation using an G with respect to V str D . It can be seen that with increasing V str G , the interplay between NBTI and HCD leads to the formation of a minimum in ΔV AS th at V str D = −0.5 V. Such a behavior has already been discussed in [13] and [14]. Furthermore, as also shown in Fig.…”

Section: Resultssupporting

confidence: 66%

“…As an example, for t str = 1.11 ks, the drift minimum forms around V str D = −0.5 V for all V G,stress conditions. Such a degradation minimum has already been reported and discussed in [13] and [14]. This behavior was explained by competing processes contributing to the degradation: while sweeping V str D from…”

Section: A Impact Of Mixed Nbti/hc Stress On Large-area Pmosfet Parameterssupporting

confidence: 59%

“…The bottom panels show the threshold voltage shift after stress (ΔV AS th = |ΔV th (t rec = 5 ms)|) on the left-hand side and the recovery (R = |ΔV th (t rec = 5 ms) −ΔV th (t rec = 1.11 ks)|) on the right-hand side for different V strG with respect to V str D . It can be seen that with increasing V str G , the interplay between NBTI and HCD leads to the formation of a minimum in ΔV AS th at V str D = −0.5 V. Such a behavior has already been discussed in[13] and[14]. Furthermore, as also shown in Fig.2, R reduces with increasing |V str D |.…”

supporting

confidence: 65%

“…However, in circuits, transistors are rarely subjected to idealized BTI or HC conditions. Nevertheless, only a limited number of studies are available on the interplay between BTI and HCD [13]- [17] under mixed BTI/HC stress conditions schematically illustrated in Fig. 1.…”

Section: Impact Of Mixed Negative Bias Temperature Instability and Hot Carrier Stress On Mosfetmentioning

confidence: 99%

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Impact of Mixed Negative Bias Temperature Instability and Hot Carrier Stress on MOSFET Characteristics—Part I: Experimental

Ullmann

Jech

Puschkarsky

et al. 2019

IEEE Trans. Electron Devices

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Bias temperature instability (BTI) and hotcarrier degradation (HCD) are among the most important reliability issues but are typically studied independently in an idealized setting. However, even though it is well understood that mixed BTI/HC degradation corresponds to a realistic scenario, there is only a limited number of studies available on the impact of mixed stress conditions. In this first part of the work, we present a thorough experimental study of the impact of mixed stress conditions on SiON pMOSFET characteristics, which contain a study at the single defect level. We focus on the contribution of single defects to the recoverable component of degradation. From an electrostatic point of view, recovery after mixed negative BTI (NBTI)/HC stress is typically attributed to charge carrier emissions by oxide defects near the source, which have been charged during stress. However, the experimental characterization of recovery after different stress conditions provides strong evidence that even defects located in the vicinity of the source can remain uncharged after mixed NBTI/HC stress, and thus do not contribute to the recovery signal. Consequently, the recoverable component can be negligibly small after certain stress conditions, which leads to the conclusion that a simple electrostatic model does not properly describe the behavior of recovery after mixed NBTI/HC stress.Index Terms-Device reliability, hot-carrier degradation (HCD), mixed-mode stress, negative bias temperature instability (NBTI), pMOSFET, single oxide defects, timedependent defect spectroscopy (TDDS). I. INTRODUCTIONB IAS temperature instability (BTI) and hot-carrier degradation (HCD) affect the performance of metal-oxide-

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Section: Resultssupporting

confidence: 66%

Section: A Impact Of Mixed Nbti/hc Stress On Large-area Pmosfet Parameterssupporting

confidence: 59%

supporting

confidence: 65%

Section: Impact Of Mixed Negative Bias Temperature Instability and Hot Carrier Stress On Mosfetmentioning

confidence: 99%

See 2 more Smart Citations

Impact of Mixed Negative Bias Temperature Instability and Hot Carrier Stress on MOSFET Characteristics—Part I: Experimental

Ullmann

Jech

Puschkarsky

et al. 2019

IEEE Trans. Electron Devices

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“…The impact of NBTI degradation on MOS circuit behavior is generally studied for digital circuit performance degradation [1]- [8], as digital circuits are usually subjected to enhanced gate and drain voltages which are comparable to the supply voltage. In addition to digital circuits, NBTI is reported to be a major reliability concern for analog circuits as has been shown by device-level characterizations for various analog performance parameters [9]- [12].…”

Section: Introductionmentioning

confidence: 99%

NBTI Degradation and Its Impact for Analog Circuit Reliability

Jha

Reddy

Sharma

et al. 2005

IEEE Trans. Electron Devices

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Abstract-A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors.Index Terms-Analog/mixed-signal circuits, circuit lifetime, negative bias temperature instability (NBTI), pMOSFET degradation, threshold-voltage shift.

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