Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs

Abstract

We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics.

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

“…NBT stress-induced threshold voltage shifts have been found in n-type trench DMOS transistors [30]. Previous research of NBTI in power VDMOSFETs led to a rather similar finding [31,32].…”

“…However, having in mind that high negative gate bias can be used in some automotive applications for the faster turning off of the NMOS devices, rather significant NBT stress-induced threshold voltage shifts have been found in n-type trench DMOS transistors [30]. Previous research of NBTI in power VDMOSFETs led to a rather similar finding [31,32]. The dependencies of the underlying buildup of gate oxide trapped charge and interface traps on stress time under stress bias (at 150 • C) and temperature (at −/+40 V) are illustrated in Figures 6-8.…”

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

“…In practical circuit operations, devices experience various reliability issues, triggering non-ideal effects such as circuit functional aging and failure. As shown in Figure 1 , taking a typical inverter circuit as an example, devices undergo three typical biasing conditions: gate voltage (V gs ) > 0 V, drain voltage (V ds ) = 0 V; |V gs | > 0 V, |V ds | > 0 V and V gs = 0 V, |V ds | > 0 V. The degradation phenomena observed in NMOS or PMOS devices under the bias condition of |V gs | > 0 V, V ds = 0 V are, respectively, termed positive bias temperature instability (PBTI) [ 24 , 25 , 26 ] and negative bias temperature instability (NBTI) [ 27 , 28 , 29 , 30 , 31 , 32 , 33 ]. The degradation phenomenon observed when the device is under the bias condition of |V gs | > 0 V, |V ds | > 0 V is referred to as hot carrier degradation (HCD) [ 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 ].…”

Logical Resolving-Based Methodology for Efficient Reliability Analysis

“…When SP is equal to “1”, the device will be frequently stressed throughout its lifetime and the timing degradation will significantly increase, as shown in the trend at the end of the curve in Figure 1 . The reason is that the aging defects are partially healed during stress-free phases, but the recovery will be just enough to ignore as the SP approaches “1” [ 8 ]. Therefore, accurately evaluating SP is essential for aging analysis on the digital circuit [ 9 , 10 ].…”