Impact of Oxide Thickness on Gate Capacitance—A Comprehensive Analysis on MOSFET, Nanowire FET, and CNTFET Devices

Sinha, Sanjeet Kumar; Chaudhury, Saurabh

doi:10.1109/tnano.2013.2278021

Cited by 73 publications

(25 citation statements)

References 11 publications

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“…. Through result shown in Fig.1 and Fig.2, we can conclude that in nanoscale regime, Nanowire FET has advantage over MOSFET due to lesser and lesser quantum capacitance, while in MOSFET the value of quantum capacitance goes on increasing which leads increased propagation delay and hence performance degradation [9].…”

Section: Mosfet and Nanowire -Fetmentioning

confidence: 92%

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Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices

Sinha

Kumar

Chaudhury

2015

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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In nano-scaled devices, as the voltage is scaled down in order to achieve low power which further causes the threshold voltage also to be scaled in order to meet the performance requirements. However, reduction in threshold voltage leads to increased leakage power in short channel devices. Nanowire FET (NW-FET) is a possible alternative to minimize short channel effects in traditional MOS structure. In this paper we have justified the advantage of naowire FET over MOSFET by varying oxide thickness. Then we have seen the impact of channel length over characteristics of NW-FET with Si, Ge and GaAs as channel materials. With nanoHUB simulation, we found that, while reducing the channel length from 12 nm to 4 nm, the drain current and subthreshold swing (SS) at a very small Vg increases due to tunnelling effect. In NW-FET, the drain current is normalized by the circumference of the nanowire and the SS is defined as the inverse of the slope of log 10 Id vs Vg curve. We have also simulated and analyzed that the electron density at channel region while reducing the channel length.

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Section: Mosfet and Nanowire -Fetmentioning

confidence: 92%

“…Whereas in case of nanowire FET under identical simulating condition as in case of MOSFET, the quantum capacitance decreases as the oxide thickness reduces from 1.5 nm to 0.7 nm, at gate voltage from 0.5 V and above. [9]. .…”

Section: Mosfet and Nanowire -Fetmentioning

confidence: 99%

Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices

Sinha

Kumar

Chaudhury

2015

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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“…The results presented are for 1.5 nm oxide thickness; however, there is great impact of oxide thickness on quantum gate capacitance. 33 …”

Section: Quantum Capacitance Modelmentioning

confidence: 99%

Circuit Compatible Model for Electrostatic Doped Schottky Barrier CNTFET

Singh

Khosla

Raj

2016

Journal of Elec Materi

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This paper proposes a circuit compatible model for electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET). The proposed model is an extension of the Schottky barrier carbon nanotube field effect transistor (SBCNTFET) to ED-SBCNTFET by adding polarity gates, which are used to create electrostatic doping. In ED-SBCNTFET, electrostatic doping is responsible for a fermi level shift of source and drain regions. A mathematical relation has been developed between fermi level shift and polarity gate bias. Both current-voltage (I-V) and capacitance-voltage (C-V) characteristics have been efficiently modeled. The results are compared with the reported semi-classical model and simulations from NanoTCAD ViDES for validation. The proposed model is much faster than numerical models as it denies self consistent equations. Finally, circuit application is demonstrated by simulating inverter using the proposed model in HSPICE.

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“…However, in nanoscale devices, as the oxide thickness approaches the nanometer regime, the oxide capacitance C ox becomes comparable to the inversion layer capacitance C inv which means that the quantum capacitance C Q and the centroid capacitance C cent start to affect the gate capacitance [8]. The centroid capacitance C cent is related to the average physical distance of the electrons present in the quantum well/2DEG from the metal gate [2].…”

Section: Quantum Capacitance In Heterostructuresmentioning

confidence: 99%

Impact of oxide thickness on gate capacitance – Modelling and comparative analysis of GaN-based MOSHEMTs

2015

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In this paper, we have developed a mathematical model to predict the behaviour of gate capacitance and threshold voltage with nanoscale variation of oxide thickness in AlInN/GaN and AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). The results obtained from the model are compared with the TCAD simulation results to validate the model. It is observed that AlInN/GaN MOSHEMT has an advantage of significant decrease in gate capacitance up to 0.0079 pF/μm 2 with increase in oxide thickness up to 5 nm as compared to conventional AlGaN/GaN MOSHEMT. This decrease in gate capacitance in AlInN/GaN MOSHEMT reduces the propagation delay and hence improves the RF performance of the device.

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Impact of Oxide Thickness on Gate Capacitance—A Comprehensive Analysis on MOSFET, Nanowire FET, and CNTFET Devices

Cited by 73 publications

References 11 publications

Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices

Si/Ge/GaAs as channel material in nanowire-FET structures for future semiconductor devices

Circuit Compatible Model for Electrostatic Doped Schottky Barrier CNTFET

Impact of oxide thickness on gate capacitance – Modelling and comparative analysis of GaN-based MOSHEMTs

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