Impact of oxygen plasma postoxidation process on Al2O3/<i>n</i>-In0.53Ga0.47As metal-oxide-semiconductor capacitors

Lechaux, Yoann; Fadjie-Djomkam, A. B.; Bollaert, S.; Wichmann, Nicolas

doi:10.1063/1.4963656

Cited by 7 publications

(3 citation statements)

References 29 publications

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“…The sample is then transferred into the atomic layer depositon reactor where 2 nm of Al 2 O 3 is formed via 20 cycles utilizing trimethyl aluminum (TMA) precursor and H 2 O oxidizing agent. Subsequently, the process continues by applying an in situ oxygen plasma treatment that, as reported in [17,18], improves the III-V MOS capacitance response. In essence, this creates an oxide layer lying above the III-V/oxide interface blocking the diffusion of oxygen species that usually occurs during the post-deposition annealing step.…”

Section: Methodsmentioning

confidence: 99%

Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy

et al. 2018

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In this paper we report on the fabrication and electrical characterization of InAs-on-nothing metal-oxide-semiconductor field-effect transistor composed of a suspended InAs channel and raised InAs n+ contacts. This architecture is obtained using 3D selective and localized molecular beam epitaxy on a lattice mismatched InP substrate. The suspended InAs channel and InAs n+ contacts feature a reproducible and uniform shape with well-defined 3D sidewalls. Devices with 1 μm gate length present a saturation drain current (IDsat) of 300 mA mm−1 at VDS = 0.8 V and a trans-conductance (GM) of 120 mS mm−1 at VDS = 0.5 V. In terms of electrostatic control, the devices display a minimal subthreshold swing of 110 mV dec−1 at VDS = 0.5 V and a small drain induced barrier lowering of 50 mV V−1.

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Section: Methodsmentioning

confidence: 99%

Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy

et al. 2018

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“…Обработка структуры полупроводник/диэлектрик в кислородной плазме после атомнослоевого осаждения позволила существенно уменьшить окисление поверхности полупроводника в процессе последующего отжига (рис. 20) и тем самым существенно улучшить электронные характеристики формирующихся интерфейсов [124,346].…”

Section: модификация интерфейсов полупроводник/диэлектрикunclassified

Модификация Атомной И Электронной Структуры Поверхности Полупроводников А-=sup=-Iii-=/Sup=-В-=sup=-v-=/Sup=- На Границе С Растворами Электролитов О Б З Ор

Лебедев¹

2020

Физика И Техника Полупроводников

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Recent experimental and theoretical results on modification of the surface atomic and electronic structure of various III–V semiconductor with electrolyte solutions are reviewed. The relationship between the chemical and charge transfer processes that proceed at the semiconductor/electrolyte interfaces and accompanying modification of the semiconductor surface atomic and electronic structure is revealed. Advances in the application of electrolyte solutions for modification of the semiconductor nanostructures and device performance are discussed.

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“…Indeed, III-V MOSFETs can work at V DS lower than 0.5 V and deliver I ON currents near 1 A/mm, 6,7 but with a large value of SS, while reliability is still a drawback due to the degradation of the gate oxide. 8 As an alternative, we explore III-V I-MOSFETs for ultra-low power logic applications, because they can lead to an improvement on the reliability with respect to Si I MOSFETs (by reducing the carrier energy) and to a decrease of V DS due to the higher II coefficient of III-V high-mobility narrow-bandgap materials. However, in III-V structures tunneling tends to appear for lower V DS than II processes, and tunnel-FETs (TFETs) [9][10][11] are the mainstream approach for ultra-low SS digital applications.…”

Section: Introductionmentioning

confidence: 99%

Impact ionization and band-to-band tunneling in InxGa1-xAs PIN ungated devices: A Monte Carlo analysis

Vasallo

González

Talbo

et al. 2018

Journal of Applied Physics

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III-V Impact-ionization (II) metal-oxide-semiconductor FETs (I-MOSFETs) and tunnel FETs (TFETs) are being explored as promising devices for low-power digital applications. To assist the development of these devices from the physical point of view, a Monte Carlo (MC) model which includes impact ionization processes and band-to-band tunneling is presented. The MC simulator reproduces the I-V characteristics of experimental ungated In 0.53 Ga 0.47 As 100 nm PIN diodes, in which tunneling emerges for lower applied voltages than impact ionization events, thus being appropriate for TFETs. When the structure is enlarged up to 200 nm, the ON-state is achieved by means of impact ionization processes; however, the necessary applied voltage is higher, with the consequent drawback for low-power applications. In InAs PIN ungated structures, the onset of both impact ionization processes and band-to-band tunneling takes place for similar applied voltages, lower than 1 V; thus they are suitable for the design of low-power I-MOSFETs.

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Impact of oxygen plasma postoxidation process on Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors

Cited by 7 publications

References 29 publications

Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy

Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy

Модификация Атомной И Электронной Структуры Поверхности Полупроводников А-=sup=-Iii-=/Sup=-В-=sup=-v-=/Sup=- На Границе С Растворами Электролитов О Б З Ор

Impact ionization and band-to-band tunneling in InxGa1-xAs PIN ungated devices: A Monte Carlo analysis

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