Impact of Pocket Doping On the Performance of Planar SOI Junctionless Transistor

Bashir, Faisal; Murshid, Asim M.; Khanday, Farooq Ahmad; Banday, M. Tariq

doi:10.1007/s12633-020-00568-1

Cited by 4 publications

(1 citation statement)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the scaling of such devices below 32/22nm technology node becomes difficult due to gate oxide tunneling, parasitic and short channel effects (SCE) [3]. Various solutions have been put forward to overcome such difficulties [4][5]. Planar structure with an ultra-thin body SOI MOSFET, tri-gate structures etc.…”

Section: Introductionmentioning

confidence: 99%

2-D Design of Double Gate Schottky Tunnel MOSFET for High-Performance Use in Analog/RF Applications

et al. 2021

Self Cite

View full text Add to dashboard Cite

In this work, a new structure of Schottky tunneling MOSFET has been designed and simulated. The proposed device structure uses floating gates and dual material main gates to counter short channel effects and to improve RF/Analog figures of merit for low power design applications. The use of floating gates modulates the Schottky barrier width, hence improves the ON state and RF/Analog figures of merit performance of the proposed device in comparison to a conventional device. A significantly high ION (1.231×10 -4 A/µm) and ION/IOFF ratio (2.52×10 5 ) is achieved in the proposed ST-MOSFET in comparison to conventional ST-MOSFET having ION (1×10 -7 A/µm) and ION/IOFF ratio (1×10 2 ). It has been observed that there is more than 100 times improvement in cutoff frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), gain bandwidth product (GBP) and max oscillation frequency (fmax) in comparison to conventional ST-MOSFET. In addition, there are reductions of 98% and 33.33% in switching ON and OFF delays respectively in the proposed devicebased inverter circuit in comparison to conventional ST-MOSFET based inverter circuit. Furthermore, the proposed ST-MOSFET device does not require any highly doped regions, hence does not have any doping related issues.

show abstract

Section: Introductionmentioning

confidence: 99%