Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)

Yang, Xiaoqiao; Li, Xianglong; Liu, Ziyu; Sun, Yabin; Liu, Yun; Shi, Yanling

doi:10.1109/ted.2022.3176835

Cited by 16 publications

(4 citation statements)

References 37 publications

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“…Similarly, to consider their possible interaction among six factors, we do generate all random distributions for all factors at the same time. Notably, in contrast to the studies reported in [26], [27], where they assessed the impact of each factor independently, we examine both individual and simultaneous effects. This approach enables us to consider their interaction among all factors owing to their annihilation and enhancement effects.…”

Section: -D Device Simulation and Pve Parametersmentioning

confidence: 99%

“…Hence, it is imperative to acknowledge that process variations wield a substantial influence on the holistic operational performance of circuits employing these devices. On the other hand, process variation effect (PVE) and intrinsic parameter fluctuation (IPF) consists of work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF), are crucial in design and fabrication of CMOS devices [6]- [25]; in particular, for emerging CFET devices [26]- [28]. For examples, [7]- [9], [9]- [14], [14]- [19], and [13], [14], [20]- [25], were reported for planar MOSFETs, FinFETs, GAA nanowire MOSFETs, and GAA NS MOSFETs, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…These variations serve as a formidable barrier to the continued scaling of technology nodes, exerting their influence on critical aspects including SCE, timings, and power consumption parameters. Two factors of PVE: line edge roughness and gate edge roughness were individually studied by Yang et al for CFETs [26], [28]; however, impacts of PVE on electrical characteristic and power fluctuations have not been well examined yet for CFET devices and circuits. Thus, it will be an interesting study for us to statistically explore device characteristics and power fluctuations of CFETs induced by various factors of PVE.…”

Section: Introductionmentioning

confidence: 99%

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Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Kola,

2023

IEEE Open J. Nanotechnol.

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Characteristic variability induced by process variation effect (PVE) is one of technological challenges in semiconductor industry. In this work, we computationally study electrical characteristic and power fluctuations induced by six factors of PVE of the gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field-effect-transistors (CFETs) which are formed by vertically stacking n-FET on top of p-FET. Among the six factors, NS thickness (TNS), NS width (WNS), and gate length (LG) are identified as crucial factors contributing to large variations in device characteristics. The p-FET exhibits substantial off-state current fluctuation (about 151%) due to the bottom parasitic channel leakages. Compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (up to 148%). If we assume that each factor of PVE has the same probability distribution as the others and all are mutually independent, the statistical sum of their power fluctuations will exhibit more than 50% overestimations, compared with the results when all factors are considered simultaneously.

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Section: -D Device Simulation and Pve Parametersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Kola,

2023

IEEE Open J. Nanotechnol.

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“…Another aspect to optimize is the device variability, which can result from several sources including, but not limited to, line-edge roughness, gate-edge roughness, non-uniform work function metal deposition, and random dopant fluctuations. A recent study analyzes these variability and proposes solution for a complementary GAA nanosheet FET structure [32].…”

Section: Current Challengesmentioning

confidence: 99%

A Review of the Gate-All-Around Nanosheet FET Process Opportunities

Mukesh

Zhang

2022

Electronics

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In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed.

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Multivalued DRAM

Karmakar

2023

J. Electron. Mater.

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Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)

Cited by 16 publications

References 37 publications

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

A Review of the Gate-All-Around Nanosheet FET Process Opportunities

Multivalued DRAM

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