Impact of progressive oxide soft breakdown on metal oxide semiconductor parameters: Experiment and modeling

Abstract

Articles you may be interested inModel for the voltage and temperature dependence of the soft breakdown current in ultrathin gate oxides J. Appl. Phys. 97, 014104 (2005); 10.1063/1.1827343 Comparison of oxide breakdown progression in ultra-thin oxide silicon-on-insulator and bulk metal-oxidesemiconductor field effect transistors J. Appl. Phys. 96, 3473 (2004); 10.1063/1.1776640 Size difference in dielectric-breakdown-induced epitaxy in narrow n-and p-metal oxide semiconductor field effect transistors Appl. Phys. Lett. 83, 2940 (2003); 10.1063/1.1616195 Modeling random telegraph signals in the gate current of metal-oxide-semiconductor field effect transistors after oxide breakdown J. Appl. Phys. 94, 703 (2003); 10.1063/1.1579134Low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors undergoing soft breakdownThe impact of a soft breakdown-induced leaky weak spot occurring in the channel has been analyzed by two dimensional simulations of a metal oxide semiconductor field effect transistor within the charge sheet approximation. The model proves very efficient in reproducing the device characteristics variations after soft breakdown ͑SBD͒ and enables to properly interpret the correlation observed between device parameter shift ͑e.g., threshold voltage͒ and stress-induced gate leakage current. A partitioning study allows us to extract an expression for the channel debiasing at V d Ͼ 0 and to discriminate each impact of SBD on device characteristics.

Unified Compact Model of Soft Breakdown Oxide Degradation and Its Impact on CMOS Circuits Reliability

“…Moreover, we proved again the existing logarithmical relation between gate current increase and threshold voltage deviation [8], first demonstrated by [3], and extend its applicability through statistical studies of its parameters deviations; measurement and empirical laws are presented in Fig. 2…”

“…There is a more fundamental reason for this channel current illustrated by (2), namely the so called channel debiasing [8]. Indeed, a local leakage due to the formation of a conduction path through the oxide induces channel charges reorganization all around and, by turn, reduces the channel bias.…”

New Insights Into Oxide Breakdown Current Partitioning Analysis for MOS Devices

“…But a stressed device can undergo several BD occurrences. Indeed, [7], [8] show experimental results with a 1000 s progressiveness span under stress before hard BD (HBD) might occur. We performed measurement on PMOS devices from the 45 nm node featuring a 40nm channel length and 1 µm width with polysilicon gate and silicon nitrided oxide.…”

“…As explained in [7], this channel conductivity lowering is responsible for the observed threshold voltage shift due to BD. Indeed, a correlation has been shown between the threshold voltage shift and the localized leakage intensity corresponding to charge reorganization around the BD spot [8], leading to the channel debiasing. Since the extra gate leakage has been normalized after the first BD occurrence, one can reasonably assume that this correlation is governed by the BD dynamics and not the previous degradations.…”