Impact of RET on physical layouts

Abstract

In this paper, we briefly describe the lithography developments known as RET (Resolution Enhancement Technologies), which include off-axis illumination in litho tools, Optical and Process Correction (OPC), and phase shifting masks (PSM). All of these techniques are adopted to allow ever smaller features to be reliably manufactured, and are being generally adopted in all manufacturing below 0.25 microns. However, their adoption also places certain restrictions on layouts. We explore these restrictions, and then provide suggestions for layout practices that will facilitate the use of these technologies, especially the generation of a clean "target" layout for use as input layers for photomask preparation, and the use of verification tools that use process simulation.

Design rule optimization of regular layout for leakage reduction in nanoscale design

“…Off axis illumination (OAI) technique is applied as OAI amplifies certain pitch at the cost of others. This phenomena is called "Forbidden" pitch [13,14]. In order to overcome this OAI limitation, sub-resolution assist feature (SRAF) [5] is accounted in our optimization.…”

The impact of the nanoscale on computing systems

“…For example, as feature sizes become smaller than the illumination wavelength used in photolithography, resolution enhancement techniques (RETs) must be used to ensure printability. RETs are already restricting layouts that are manufacturable [8]- [11]. ChemicalMechanical Polishing (CMP) is another example of a process/layout interaction [12].…”